From mboxrd@z Thu Jan  1 00:00:00 1970
From: Kishon Vijay Abraham I <kishon@ti.com>
Date: Tue, 10 Oct 2017 11:18:53 +0530
Subject: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a
 cache aligned manner
In-Reply-To: <0ded15f3-cb75-3fac-b830-36a176509004@ti.com>
References: <1505819741-29843-1-git-send-email-faiz_abbas@ti.com>
 <e7d0cc66-63b5-e043-aeca-8967f5b73e0c@denx.de>
 <78dff6f0-6381-3aba-4b7d-f8146404a9f8@ti.com>
 <807dfdf2-d002-e202-7e4b-054479b95ef1@denx.de>
 <eb0126fa-01b4-cab0-bae4-864a0d2e1953@ti.com>
 <8da50d1d-ff7e-09e0-da1d-52a616630cb5@denx.de>
 <842316a1-a92d-8d76-f602-c95627283524@ti.com>
 <d47835f7-21a5-aece-ad79-ac578f0d376e@denx.de>
 <7669ca56-7204-b4b5-f3d0-88a14313e483@ti.com>
 <0ded15f3-cb75-3fac-b830-36a176509004@ti.com>
Message-ID: <97aac252-e555-a24a-e236-96fa68540bea@ti.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

Hi,

On Tuesday 10 October 2017 11:07 AM, Faiz Abbas wrote:
> +Kishon
> 
> On Friday 06 October 2017 05:03 PM, Faiz Abbas wrote:
>> Hi,
>>
>> On Thursday 05 October 2017 04:57 PM, Marek Vasut wrote:
>>> On 10/04/2017 03:11 PM, Faiz Abbas wrote:
>>>> Hi,
>>>>
>>>> On Wednesday 04 October 2017 06:01 PM, Marek Vasut wrote:
>>>>> On 10/04/2017 12:51 PM, Faiz Abbas wrote:
>>>>>> Hi,
>>>>>> On Tuesday 03 October 2017 06:48 PM, Marek Vasut wrote:
>>>>>>> On 10/03/2017 03:17 PM, Faiz Abbas wrote:
>>>>>>>> Hi,
>>>>>>>> On Tuesday 03 October 2017 05:34 PM, Marek Vasut wrote:
>>>>>>>>> On 09/19/2017 01:15 PM, Faiz Abbas wrote:
>>>>>>>>>>  
>>>>>>>>>> -	dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
>>>>>>>>>> +	dwc3_flush_cache((uintptr_t)dwc->ep0_trb_addr, sizeof(*trb) * 2);
>>>>>>>>>
>>>>>>>>> Why *2 ?
>>>>>>>>
>>>>>>>> Because its allocated as sizeof(*dwc->ep0_trb) * 2 below. This is not
>>>>>>>> strictly required as dwc3_flush_cache() rounds up the size to
>>>>>>>> CACHELINE_SIZE but from a caller POV, flush everything we allocated.
>>>>>>>
>>>>>>> Can the other TRB be in use ? Maybe aligning the TRBs to cacheline size
>>>>>>> would be better ?
>>>>>>>
>>>>>> A single trb is 16 bytes in size and two of them are allocated
>>>>>> contiguously.
>>>>>
>>>>> Why are two allocated continuously ? (I am not dwc3 expert)

The TRB's should be allocated contiguously for dwc3 and only the base of the
entire TRB table is programmed in the HW.
 ________________ <------------------ TRB table base address
|     TRB0       |
|________________|
|     TRB1       |
|________________|
|     TRB2       |
|________________|
|     TRBn       |
|________________|


>>>>
>>>> Neither am I. I did try to pad to the dwc_trb structure such that each
>>>> trb is 64 bytes in size but this leads to failures when testing. I
>>>> didn't get a chance to debug this though. I suspect its because the code
>>>> expects the trbs to be contiguous and/or 16 bytes in size.

It's not the code but it's the HW.

Thanks
Kishon