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From: Dinh Nguyen <dinguyen@kernel.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 10/11] arm: dts: socfpga: Add dts for Stratix 10 socdk
Date: Tue, 6 Sep 2016 09:14:49 -0500	[thread overview]
Message-ID: <97f372c8-31ea-5793-6c67-b75ccbfbd360@kernel.org> (raw)
In-Reply-To: <1473156209-5734-11-git-send-email-clsee@altera.com>



On 09/06/2016 05:03 AM, Chin Liang See wrote:
> Add device tree for Stratix 10 SoC development kit
> 
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
> Acked-by: Marek Vasut <marex@denx.de>
> ---
>  arch/arm/dts/Makefile                    |  3 +-
>  arch/arm/dts/socfpga_stratix10_socdk.dts | 63 ++++++++++++++++++++++++++++++++
>  2 files changed, 65 insertions(+), 1 deletion(-)
>  create mode 100755 arch/arm/dts/socfpga_stratix10_socdk.dts
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 223124e..c5e2d3c 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -127,7 +127,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
>  	socfpga_cyclone5_sockit.dtb			\
>  	socfpga_cyclone5_socrates.dtb			\
>  	socfpga_cyclone5_sr1500.dtb			\
> -	socfpga_cyclone5_vining_fpga.dtb
> +	socfpga_cyclone5_vining_fpga.dtb		\
> +	socfpga_stratix10_socdk.dtb
>  
>  dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
>  dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
> new file mode 100755
> index 0000000..7465358
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -0,0 +1,63 @@
> +/*
> + *  Copyright (C) 2016 Intel Corporation
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +/dts-v1/;
> +/* First 4KB has trampoline code for secondary cores. */
> +/memreserve/ 0x00000000 0x0001000;

ARM64 should be using PSCI for SMP. I don't think the trampoline code is
needed.

> +#include "skeleton.dtsi"
> +
> +/ {
> +	model = "Altera SOCFPGA Stratix 10 SoC Development Kit";
> +	compatible = "altr,socfpga-stratix10", "altr,socfpga";
> +
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200";
> +	};
> +
> +	memory {
> +		name = "memory";
> +		device_type = "memory";
> +		reg = <0x0 0x40000000>; /* 1GB */
> +	};

are you sure we still have only 1GB?

> +
> +	regulator_3_3v: 3-3-v-regulator {
> +		compatible = "regulator-fixed";
> +		regulator-name = "3.3V";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +	};
> +
> +	soc {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		device_type = "soc";
> +		ranges;
> +
> +		mmc0: dwmmc0 at 0xff808000 {
> +			compatible = "altr,socfpga-dw-mshc";
> +			reg = <0xff808000 0x1000>;
> +			interrupts = <0 139 4>;

This interrupt number is not correct. Copy/paste error from Cyclone5?
For S10, I think it's 96.

> +			num-slots = <1>;
> +			broken-cd;
> +			bus-width = <4>;
> +			fifo-depth = <0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			cap-mmc-highspeed;
> +			cap-sd-highspeed;
> +			drvsel = <3>;
> +			smplsel = <0>;
> +			status = "okay";
> +			u-boot,dm-pre-reloc;
> +			vmmc-supply = <&regulator_3_3v>;
> +			vqmmc-supply = <&regulator_3_3v>;
> +		};
> +	};
> +};
> 

Dinh

  reply	other threads:[~2016-09-06 14:14 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-06 10:03 [U-Boot] [PATCH v2 00/11] Add support for Stratix 10 SoC Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 01/11] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address Chin Liang See
2016-09-06 14:29   ` Dinh Nguyen
2016-09-07 13:35     ` Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 02/11] arm: socfpga: rstmgr: Add Reset Manager for Stratix 10 Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 03/11] arm: socfpga: rstmgr: Separate the " Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 04/11] arm: socfpga: clkmgr: Separate the Clock " Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 05/11] arm: socfpga: fpgamgr: Disable FPGA " Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 06/11] arm: socfpga: misc: Separate the misc.c " Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 07/11] arm: socfpga: sysmgr: Fix casting warning when enabling ARM64 Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 08/11] arm: socfpga: mmu: Add memory map layout for Stratix 10 SoC Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 09/11] arm: socfpga: stratix10: Add board directory for Stratix 10 socdk Chin Liang See
2016-09-06 14:30   ` Dinh Nguyen
2016-09-07 13:35     ` Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 10/11] arm: dts: socfpga: Add dts " Chin Liang See
2016-09-06 14:14   ` Dinh Nguyen [this message]
2016-09-07 13:42     ` Chin Liang See
2016-09-06 10:03 ` [U-Boot] [PATCH v2 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit Chin Liang See
2016-09-06 14:32   ` Dinh Nguyen
2016-09-07 13:42     ` Chin Liang See

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