From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7421CC7EE22 for ; Wed, 10 May 2023 09:10:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E764A8601B; Wed, 10 May 2023 11:10:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="ceKjUNL2"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 820C485D0B; Wed, 10 May 2023 11:10:20 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2104A8601B for ; Wed, 10 May 2023 11:10:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rogerq@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 311D163C7E; Wed, 10 May 2023 09:10:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2A0CFC433D2; Wed, 10 May 2023 09:10:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683709815; bh=2HP+sga4bezXx0lbypiVKMtXAen7UVUXri/rUTs+rNs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=ceKjUNL2Qm3fKFtMOZi793ICfhN63jLPNTyymWtCQYIavQnjM4AeF3ij0FMmRIv/7 otQRFRFe+JFGtnuiOQXC2s4HGsfmylsfTj89uzfICvE1NonDl/YlJFgi5rxgK1zFeq 6ZBVQ9lxrsk9tO3imGveFLaH6j2b16N3XfoSCxqKNFbDKPTeNZ8pZGGIXNPYBXBXjb qGzQItzxjnmJ4VLC46drDaXhe1kN1nv/p/Zm+ixkFAdCoU1nwyYOhUwCmvmdecT7mE QkZZcvjhV0tRknRitFoqWVLRMscYwnqVdPdsNEytLhnpGT0dEHsb51QOGZPQwjeu90 JAr4r/tJnOe3w== Message-ID: <9a47a2d2-c3ca-946c-db4e-72f26eaaf1ad@kernel.org> Date: Wed, 10 May 2023 12:10:11 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [EXTERNAL] Re: [PATCH] usb: cdns3: gadget.c: Set fast access bit Content-Language: en-US To: Ravi Gunasekaran , marex@denx.de Cc: u-boot@lists.denx.de, Pawel Laszczak , Peter Chen References: <20230505121353.23486-1-r-gunasekaran@ti.com> <78903233-bb52-8ecd-ef65-df104fff069a@kernel.org> From: Roger Quadros In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean +Pawel & Peter On 09/05/2023 08:58, Ravi Gunasekaran wrote: > Hi Roger, > > On 05/05/23 6:02 pm, Roger Quadros wrote: >> Hi Ravi, >> >> On 05/05/2023 15:13, Ravi Gunasekaran wrote: >>> From: Aswath Govindraju >>> >>> When the device port is in a low power state [U3/L2/Not Connected], >>> accesses to usb device registers may take a long time. This could lead to >>> potential core hang when the controller registers are accessed after the >>> port is disabled by setting DEVDS field. Setting the fast register access >>> bit ensures that the PHY clock is keeping up in active state. >>> >>> Therefore, set fast access bit to ensure the accesses to device registers >>> are quick even in low power states. >>> >>> Signed-off-by: Aswath Govindraju >>> --- >>> drivers/usb/cdns3/gadget.c | 4 ++++ >>> 1 file changed, 4 insertions(+) >>> >>> diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c >>> index fcaeab9cc1..fddc8c931a 100644 >>> --- a/drivers/usb/cdns3/gadget.c >>> +++ b/drivers/usb/cdns3/gadget.c >>> @@ -2321,6 +2321,9 @@ static void cdns3_gadget_config(struct cdns3_device *priv_dev) >>> writel(USB_IEN_INIT, ®s->usb_ien); >>> writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, ®s->usb_conf); >>> >>> + /* Set the Fast access bit */ >>> + writel(PUSB_PWR_FST_REG_ACCESS, &priv_dev->regs->usb_pwr); >>> + >> >> Should this be done in cdns3_gadget_udc_start() so it is symmetric? >> > > cdns3_gadget_config() is called in cdns3_gadget_udc_start() and > cdns3_gadget_resume(). These settings seems to be needed during resume > as well. But this bit was never cleared in suspend so why do you need to set it again it in resume? The commit log says that this bit must be kept set in low power states. > >>> cdns3_configure_dmult(priv_dev, NULL); >>> >>> cdns3_gadget_pullup(&priv_dev->gadget, 1); >>> @@ -2378,6 +2381,7 @@ static int cdns3_gadget_udc_stop(struct usb_gadget *gadget) >>> >>> /* disable interrupt for device */ >>> writel(0, &priv_dev->regs->usb_ien); >>> + writel(0, &priv_dev->regs->usb_pwr); >>> writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf); >>> >>> return ret; >>> >>> base-commit: a25dcda452bf6a6de72764a8d990d72e5def643d >> -- cheers, -roger