From mboxrd@z Thu Jan 1 00:00:00 1970 From: Grant Erickson Date: Mon, 28 Apr 2008 14:47:32 -0700 Subject: [U-Boot-Users] [PATCH v2] PPC405EX(r) ECC and SDRAM Initialization Clean-ups In-Reply-To: <20080428212741.B6CE0248A6@gemini.denx.de> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 4/28/08 2:27 PM, Wolfgang Denk wrote: > In message <1209401636-9846-1-git-send-email-gerickson@nuovations.com> you > wrote: >> The primary goal of these changes is to unify some of the low-level >> SDRAM and ECC initialization code for the PPC4xx processors that use a >> common DDR2 SDRAM controller. >> >> In particular, in the case of the 405EX[r], it must initialize SDRAM >> before a primordial stack is available since OCM doesn't exist and the >> data cache does not work for such a purpose. As a consequence, the ECC >> (and SDRAM) initialization code must be stack-free. > > Stefan already asked this... I would also like to understand why the > data cache cannot be used for initial RAM as we do on so many other > systems? Agreed. The changes were based on the comments in the Kilauea and Makalu board ports indicating that this had been attempted--twice--and didn't work. I am escalating with AMCC to find out if this is a processor errata, board issue or just a programming issue that needs to be investigated further. > I hesitate to throw away good C code in favour of hard to read, hard > to maintain assembly, especially if this also breaks with some of the > U-Boot design principles. Again, agreed wholeheartedly though I have to remark that I made a particular effort to make the assembly as readable and as generalized as possible. Regards, Grant