[U-Boot-Users] [PATCH] PPC40x: Rework CFG_INIT_DCACHE_CS Block to Avoid Machine Checks

[Grant Erickson <gerickson@nuovations.com>]

On 5/18/08 1:38 PM, Wolfgang Denk wrote:
> In message <1210973711-1855-1-git-send-email-gerickson@nuovations.com> you
> wrote:
> ...
>> cpu/ppc4xx/start.S:
>>   Reworked code to handle the primordial stack and data area initialization
>> when CFG_INIT_DCACHE_CS is asserted.
> ...
>> -  * Boards like the Kilauea (405EX) don't have OCM and can't use
>> -  * DCache for init-ram. So setup stack here directly after the
>> -  * SDRAM is initialized.
>> +  * For boards that don't have OCM and can't use the data cache
>> +  * for their primordial stack, setup stack here directly after the
>> +  * SDRAM is initialized in ext_bus_cntlr_init.
> 
> Was there ever a useful explanation given why these boards should not
> be able to use DC as initial RAM?

Kilauea, Makalu and Haleakala (405EX- and 405EXr-based) can now use the data
cache for the initial stack and data area with this 'dcba' change patch.

However, no clear reason has been provided as yet from the vendor as to why
the 'dcba' addition was not historically required for the 405GP but is
required now for the 405EX[r]. Regardless, the 'dcba' should work and, going
forward, will be "more correct" on the 405GP as well.

Regards,

Grant
Principal
Nuovation System Designs, LLC

998 Alpine Terrace Suite 3
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gerickson at nuovations.com
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