From: Kumar Gala <kumar.gala@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] MPC8540 DataTLBError
Date: Sun, 16 Jan 2005 10:15:05 -0600 [thread overview]
Message-ID: <C84BE868-67D9-11D9-B3EA-000393DBC2E8@freescale.com> (raw)
In-Reply-To: <20050114210243.76646.qmail@web41411.mail.yahoo.com>
Jeff,
1. You should never take a DTLBError in u-boot, so one would think
there is an issue in your tlb setup
2. Can you get the value of DEAR out, this will help know what address
is being accessed that is causing the fault (SRR0, SRR1, and ESR) are
also useful.
3. I would expect a patch form 6/17 to be in the mainline, however
without a specific reference its very difficult to know
- kumar
On Jan 14, 2005, at 3:02 PM, Jeff Stevens wrote:
> I have a custom board with an MPC8540 processor.
> U-Boot always ends up at 0xfff81400 (DataTLBError).? I
> traced it through and found that the first time it
> enters DataTLBError is at the end of _start (in
> cpu/mpc85xx/start.S) in the loop (1:) where it is
> allocating the Initial RAM in data cache.? I traped
> the CPU before that loop and then I placed an infinite
> loop right after that loop and it never gets there.? I
> then traced back into _start right after that loop and
> told it to run again, and it went back into
> DataTLBError at a later point in the code.? So is this
> a problem with my tlb1_entry table?? I also read
> online that there was a patch submitted on 6/17/2004
> to fix this, do I need this?? I updated my U-Boot
> development tree today over CVS.? Is that patch
> already in there?? Any help would be greatly
> appreciated.? Here is my tbl1_entry.? All I did was
> alter the MPC8540ADS init.S file to get mine (I don't
> have any BCSRs or SDRAM on the LBC).
>
>
>
>
>
> tlb1_entry:
> ??????? entry_start
>
> ??????? /*
> ???????? * Number of TLB0 and TLB1 entries in the following
> table
> ???????? */
> ??????? .long 12
>
> #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
> ??????? /*
> ???????? * TLB0 ??????? ?? 4K?? Non-cacheable, guarded
> ???????? * 0xff700000?? 4K????? Initial CCSRBAR mapping
> ???????? *
> ???????? * This ends up at a TLB0 Index==0 entry, and must
> not collide
> ???????? * with other TLB0 Entries.
> ???????? */
> ??????? .long TLB1_MAS0(0, 0, 0)
> ??????? .long TLB1_MAS1(1, 0, 0, 0, 0)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT),
> 0,0,0,0,1,0,1,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT),
> 0,0,0,0,0,1,0,1,0,1)
> #else
> #error("Update the number of table entries in
> tlb1_entry")
> #endif
>
> ??????? /*
> ???????? * TLB0 ??????? 16K???? Cacheable, non-guarded
> ???????? * 0xd001_0000? 16K???? Temporary Global data for
> initialization
> ???????? *
> ???????? * Use four 4K TLB0 entries.? These entries must be
> cacheable
> ???????? * as they provide the bootstrap memory before the
> memory
> ???????? * controler and real memory have been configured.
> ???????? *
> ???????? * These entries end up at TLB0 Indicies 0x10, 0x14,
> 0x18 and 0x1c,
> ???????? * and must not collide with other TLB0 entries.
> ???????? */
> ??????? .long TLB1_MAS0(0, 0, 0)
> ??????? .long TLB1_MAS1(1, 0, 0, 0, 0)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
> 0,0,0,0,0,0,0,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
> 0,0,0,0,0,1,0,1,0,1)
>
> ??????? .long TLB1_MAS0(0, 0, 0)
> ??????? .long TLB1_MAS1(1, 0, 0, 0, 0)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 *
> 1024), 0,0,0,0,0,0,0,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 *
> 1024), 0,0,0,0,0,1,0,1,0,1)
>
> ??????? .long TLB1_MAS0(0, 0, 0)
> ??????? .long TLB1_MAS1(1, 0, 0, 0, 0)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 *
> 1024), 0,0,0,0,0,0,0,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 *
> 1024), 0,0,0,0,0,1,0,1,0,1)
>
> ??????? .long TLB1_MAS0(0, 0, 0)
> ??????? .long TLB1_MAS1(1, 0, 0, 0, 0)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 *
> 1024), 0,0,0,0,0,0,0,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 *
> 1024), 0,0,0,0,0,1,0,1,0,1)
>
>
>
> ??????? /*
> ???????? * TLB 0:????? 64M????? Non-cacheable, guarded
> ???????? * 0xfc000000?? 64M???? FLASH (First Half)
> ???????? * Out of reset this entry is only 4K.
> ???????? */
> ??????? .long TLB1_MAS0(1, 0, 0)
> ??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE),
> 0,0,0,0,1,0,1,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE),
> 0,0,0,0,0,1,0,1,0,1)
>
> ??????? /*
> ???????? * TLB 1:????? 64M????? Non-cacheable, guarded
> ???????? * 0xf8000000?? 64M???? FLASH (Second Half)
> ???????? */
> ??????? .long TLB1_MAS0(1, 1, 0)
> ??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE +
> 0x04000000), 0,0,0,0,1,0,1,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE +
> 0x04000000), 0,0,0,0,0,1,0,1,0,1)
>
> ??????? /*
> ???????? * TLB 2:?????? 256M??? Non-cacheable, guarded
> ???????? * 0x80000000?? 256M??? PCI1 MEM First half
> ???????? */
> ??????? .long TLB1_MAS0(1, 2, 0)
> ??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE),
> 0,0,0,0,1,0,1,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE),
> 0,0,0,0,0,1,0,1,0,1)
>
> ??????? /*
> ???????? * TLB 3:?????? 256M??? Non-cacheable, guarded
> ???????? * 0x90000000?? 256M??? PCI1 MEM Second half
> ???????? */
> ??????? .long TLB1_MAS0(1, 3, 0)
> ??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE +
> 0x10000000), 0,0,0,0,1,0,1,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE +
> 0x10000000), 0,0,0,0,0,1,0,1,0,1)
>
> ??????? /*
> ???????? * TLB 4:?????? 256M??? Non-cacheable, guarded
> ???????? * 0xc0000000?? 256M??? Rapid IO MEM First half
> ???????? */
> ??????? .long TLB1_MAS0(1, 4, 0)
> ??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE),
> 0,0,0,0,1,0,1,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE),
> 0,0,0,0,0,1,0,1,0,1)
>
> ??????? /*
> ???????? * TLB 5:?????? 256M??? Non-cacheable, guarded
> ???????? * 0xd0000000?? 256M??? Rapid IO MEM Second half
> ???????? */
> ??????? .long TLB1_MAS0(1, 5, 0)
> ??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE +
> 0x10000000), 0,0,0,0,1,0,1,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE +
> 0x10000000), 0,0,0,0,0,1,0,1,0,1)
>
> ??????? /*
> ???????? * TLB 6:?????? 64M???? Non-cacheable, guarded
> ???????? * 0xe000_0000? 1M????? CCSRBAR
> ???????? * 0xe200_0000? 16M???? PCI1 IO
> ???????? */
> ??????? .long TLB1_MAS0(1, 6, 0)
> ??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR),
> 0,0,0,0,1,0,1,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR),
> 0,0,0,0,0,1,0,1,0,1)
>
> #if !defined(CONFIG_SPD_EEPROM)
> ??????? /*
> ???????? * TLB 7:?????? ?? 256M DDR
> ???????? * 0x00000000?? 256M??? DDR System memory
> ???????? * Without SPD EEPROM configured DDR, this must be
> setup manually.
> ???????? * Make sure the TLB count at the top of this table
> is correct.
> ???????? * Likely it needs to be increased by two for these
> entries.
> ???????? */
> #error("Update the number of table entries in
> tlb1_entry")
> ??????? .long TLB1_MAS0(1, 8, 0)
> ??????? .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
> ??????? .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE),
> 0,0,0,0,0,0,0,0)
> ??????? .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE),
> 0,0,0,0,0,1,0,1,0,1)
> #endif
>
> ??????? entry_end
>
>
>
>
>
> ??????? ???????
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next prev parent reply other threads:[~2005-01-16 16:15 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-01-14 21:02 [U-Boot-Users] MPC8540 DataTLBError Jeff Stevens
2005-01-16 16:15 ` Kumar Gala [this message]
2005-01-18 16:13 ` Jeff Stevens
2005-01-18 17:14 ` Kumar Gala
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