[PATCH v6 07/18] video: tegra20: dc: add powergate

Svyatoslav Ryhel
2024-01-23T17:18:22Z

Add powergate use on T114 to complete resetting of DC.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
drivers/video/tegra20/tegra-dc.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index 35abb6fe46..9a18e38cd8 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -22,6 +22,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
+#include <asm/arch/powergate.h>
#include <asm/arch/pwm.h>

#include "tegra-dc.h"
@@ -32,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct tegra_dc_soc_info {
bool has_timer;
bool has_rgb;
+ bool has_pgate;
};

/* Information about the display controller */
@@ -360,6 +362,28 @@ static int tegra_lcd_probe(struct udevice *dev)

clock_disable(priv->dc_clk[0]);

+ if (priv->soc->has_pgate) {
+ uint powergate;
+
+ if (priv->pipe)
+ powergate = TEGRA_POWERGATE_DISB;
+ else
+ powergate = TEGRA_POWERGATE_DIS;
+
+ ret = tegra_powergate_power_off(powergate);
+ if (ret < 0) {
+ log_err("failed to power off DISP gate: %d", ret);
+ return ret;
+ }
+
+ ret = tegra_powergate_sequence_power_up(powergate,
+ priv->dc_clk[0]);
+ if (ret < 0) {
+ log_err("failed to power up DISP gate: %d", ret);
+ return ret;
+ }
+ }
+
/* Reset everything set before */
reset_assert(&reset_ctl);
mdelay(4);
@@ -510,16 +534,19 @@ static const struct video_ops tegra_lcd_ops = {
static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
.has_timer = true,
.has_rgb = true,
+ .has_pgate = false,
};

static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
.has_timer = false,
.has_rgb = true,
+ .has_pgate = false,
};

static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
.has_timer = false,
.has_rgb = false,
+ .has_pgate = true,
};

static const struct udevice_id tegra_lcd_ids[] = {
--
2.40.1