[PATCH v6 00/18] Add T114 video support

Svyatoslav Ryhel
2024-01-23T17:17:11Z

T114 is not that different from T30 and all T30 drivers will work
on T114 as well with some adjustments.

Patches propose general improvements for existing Tegra DC and DSI
drivers as well Tegra 114 video support (experimentl).

Commits pass buildman for tegra.

---
Changes from v5:
- backlight enable moved to the last step of setup for DSI
- parameterized V- and H-sync polarities
- added framebuffer clearing on probe to avoid glitches
- backlight enable moved after DC is fully configured
- fixed printing framebuffer pointer instead of address
- moved scdiv calculation to tegra DSI if it is used

Changes from v4:
- fixed typo in max rate to be divided (400KHz > 400MHz)

Changes from v3:
- fixed the clock divider calculation if PLLD/D2 is used
- removed unnecessary pre-configuration
- set correct video FIFO depth for DSI

Changes from v2:
- fixed image distortion on devices with 180deg rotation

Changes from v1:
- reworked patchset entirely
- diverged DC configuration per-SOC
- consolidated dc headers from different SOC gen
- initial support of DC detection (tegra has 2 DC)
- added PLLD2 support, resets and powergating
- added T114+ MIPI calibration
- added DSI detection (tegra has 2 DSI) and resets
---

Jonas Schwöbel (6):
video: tegra20: dc: fix printing of framebuffer address
video: tegra20: dc: enable backlight after DC is configured
video: tegra20: dc: clean framebuffer memory block
video: tegra20: dsi: remove pre-configuration
video: tegra20: dsi: set correct fifo depth
video: tegra20: dsi: use set_backlight for backlight only

Svyatoslav Ryhel (12):
video: tegra20: dc: diverge DC per-SOC
video: tegra20: dc: fix image shift on rotated panels
video: tegra20: consolidate DC header
video: tegra20: dc: pass DC id to internal devices
video: tegra20: dc: add PLLD2 parent support
video: tegra20: dc: add reset support
video: tegra20: dc: add powergate
video: tegra20: dc: configure behavior if PLLD/D2 is used
video: tegra20: dc: parameterize V- and H-sync polarities
video: tegra20: add MIPI calibration driver
video: tegra20: dsi: add T114 support
video: tegra20: dsi: add reset support

arch/arm/dts/tegra114-u-boot.dtsi | 13 +
arch/arm/dts/tegra114.dtsi | 4 +-
arch/arm/dts/tegra30-u-boot.dtsi | 4 +
arch/arm/dts/tegra30.dtsi | 2 +-
arch/arm/include/asm/arch-tegra/dc.h | 13 +-
arch/arm/include/asm/arch-tegra114/pwm.h | 13 +
arch/arm/include/asm/arch-tegra20/display.h | 28 --
arch/arm/include/asm/arch-tegra30/display.h | 28 --
drivers/video/tegra20/Makefile | 2 +-
drivers/video/tegra20/tegra-dc.c | 239 +++++++++++++-----
drivers/video/tegra20/tegra-dc.h | 45 ++++
drivers/video/tegra20/tegra-dsi.c | 122 ++++++++-
.../video/tegra20/tegra-dsi.h | 24 +-
drivers/video/tegra20/tegra-mipi.c | 188 ++++++++++++++
drivers/video/tegra20/tegra-pwm-backlight.c | 3 +-
15 files changed, 583 insertions(+), 145 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra114/pwm.h
delete mode 100644 arch/arm/include/asm/arch-tegra20/display.h
delete mode 100644 arch/arm/include/asm/arch-tegra30/display.h
create mode 100644 drivers/video/tegra20/tegra-dc.h
rename arch/arm/include/asm/arch-tegra30/dsi.h => drivers/video/tegra20/tegra-dsi.h (90%)
create mode 100644 drivers/video/tegra20/tegra-mipi.c

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2.40.1