Re: [PATCH v6 08/18] video: tegra20: dc: configure behavior if PLLD/D2 is used

Thierry Reding
2024-04-19T16:48:52Z

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On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause
> of this is not quite clear. This can be overcomed by further
> halving the PLLD/D2 if the target parent rate is over 800MHz.
> This way DISP1 and DSI clocks will have the same frequency. The
> shift divider in this case has to be calculated from the
> original PLLD/D2 frequency and is passed from the DSI driver.
>
> Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
> Tested-by: Ion Agorria <ion@agorria.com> # HTC One X
> Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114
> Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Microsoft Surface 2
> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> drivers/video/tegra20/tegra-dc.c | 34 +++++++++++++++++++------------
> drivers/video/tegra20/tegra-dc.h | 1 +
> drivers/video/tegra20/tegra-dsi.c | 14 +++++++++++++
> 3 files changed, 36 insertions(+), 13 deletions(-)

I'm not very familiar with these clocks, but seeing that this was
extensively tested, I guess this is okay, so:

Acked-by: Thierry Reding <treding@nvidia.com>

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