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[2003:e4:1f16:2000:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id cw11-20020a170906c78b00b00a556c5190ecsm2376320ejb.221.2024.04.19.09.05.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Apr 2024 09:05:11 -0700 (PDT) Content-Type: multipart/signed; boundary=d573c7bfac2cd8bba806a4ee804e2500e8fe42749585e4c1e0671a261c6c; micalg=pgp-sha256; protocol="application/pgp-signature" Mime-Version: 1.0 Date: Fri, 19 Apr 2024 18:05:10 +0200 Message-Id: To: "Svyatoslav Ryhel" , "Thierry Reding" , "Anatolij Gustschin" , "Simon Glass" Cc: Subject: Re: [PATCH v6 06/18] video: tegra20: dc: add reset support From: "Thierry Reding" X-Mailer: aerc 0.16.0-1-0-g560d6168f0ed-dirty References: <20240123171633.246057-1-clamor95@gmail.com> <20240123171633.246057-7-clamor95@gmail.com> In-Reply-To: <20240123171633.246057-7-clamor95@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean --d573c7bfac2cd8bba806a4ee804e2500e8fe42749585e4c1e0671a261c6c Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > Implement reset use to discard any changes which could have been > applied to DC before and can interfere with current configuration. > > Tested-by: Agneli # Toshiba AC100 T20 > Tested-by: Robert Eckelmann # ASUS TF101 > Tested-by: Andreas Westman Dorcsak # ASUS Grouper E156= 5 > Tested-by: Ion Agorria # HTC One X > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T114 > Signed-off-by: Svyatoslav Ryhel > --- > drivers/video/tegra20/tegra-dc.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/teg= ra-dc.c > index 56a23b3c97..35abb6fe46 100644 > --- a/drivers/video/tegra20/tegra-dc.c > +++ b/drivers/video/tegra20/tegra-dc.c > @@ -10,7 +10,9 @@ > #include > #include > #include > +#include > #include > +#include > #include > #include > #include > @@ -342,6 +344,7 @@ static int tegra_lcd_probe(struct udevice *dev) > struct video_uc_plat *plat =3D dev_get_uclass_plat(dev); > struct video_priv *uc_priv =3D dev_get_uclass_priv(dev); > struct tegra_lcd_priv *priv =3D dev_get_priv(dev); > + struct reset_ctl reset_ctl; > int ret; > =20 > /* Initialize the Tegra display controller */ > @@ -349,6 +352,20 @@ static int tegra_lcd_probe(struct udevice *dev) > funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); > #endif > =20 > + ret =3D reset_get_by_name(dev, "dc", &reset_ctl); > + if (ret) { > + log_err("reset_get_by_name() failed: %d\n", ret); > + return ret; > + } > + > + clock_disable(priv->dc_clk[0]); > + > + /* Reset everything set before */ > + reset_assert(&reset_ctl); > + mdelay(4); > + reset_deassert(&reset_ctl); > + mdelay(4); Are you sure this works as intended? It's been a long time since I worked on this, but I seem to recall that most of these resets are actually synchronous, so in order for them to do what they're supposed to the clock needs to be kept running. The Linux driver certainly does this differently. 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