From: "Thierry Reding" <thierry.reding@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Svyatoslav Ryhel" <clamor95@gmail.com>,
"Thierry Reding" <treding@nvidia.com>,
"Anatolij Gustschin" <agust@denx.de>,
"Simon Glass" <sjg@chromium.org>
Cc: <u-boot@lists.denx.de>
Subject: Re: [PATCH v6 01/18] video: tegra20: dc: diverge DC per-SOC
Date: Fri, 19 Apr 2024 18:34:39 +0200 [thread overview]
Message-ID: <D0O8TMM66T1F.217MXFEZPAFPA@gmail.com> (raw)
In-Reply-To: <D0O8N1XSTKTD.2J993U45EGU3@gmail.com>
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On Fri Apr 19, 2024 at 6:26 PM CEST, Thierry Reding wrote:
> On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> [...]
> > diff --git a/arch/arm/include/asm/arch-tegra114/display.h b/arch/arm/include/asm/arch-tegra114/display.h
> > new file mode 100644
> > index 0000000000..9411525799
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-tegra114/display.h
> > @@ -0,0 +1,28 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * (C) Copyright 2010
> > + * NVIDIA Corporation <www.nvidia.com>
> > + */
> > +
> > +#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
> > +#define __ASM_ARCH_TEGRA_DISPLAY_H
> > +
> > +#include <asm/arch-tegra/dc.h>
> > +
> > +/* This holds information about a window which can be displayed */
> > +struct disp_ctl_win {
> > + enum win_color_depth_id fmt; /* Color depth/format */
> > + unsigned int bpp; /* Bits per pixel */
> > + phys_addr_t phys_addr; /* Physical address in memory */
> > + unsigned int x; /* Horizontal address offset (bytes) */
> > + unsigned int y; /* Veritical address offset (bytes) */
> > + unsigned int w; /* Width of source window */
> > + unsigned int h; /* Height of source window */
> > + unsigned int stride; /* Number of bytes per line */
> > + unsigned int out_x; /* Left edge of output window (col) */
> > + unsigned int out_y; /* Top edge of output window (row) */
> > + unsigned int out_w; /* Width of output window in pixels */
> > + unsigned int out_h; /* Height of output window in pixels */
> > +};
> > +
> > +#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
>
> One of the earlier patches in the series gets rid of this per-SoC header
> file in favor of a common one. Did this end up here by mistake? It
> doesn't seem to be used.
Nevermind, my MUA sorted these patches weirdly, so it appeared as if
this was later in the series than it actually was.
Thierry
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next prev parent reply other threads:[~2024-04-19 16:34 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-23 17:16 [PATCH v6 00/18] Add T114 video support Svyatoslav Ryhel
2024-01-23 17:16 ` [PATCH v6 01/18] video: tegra20: dc: diverge DC per-SOC Svyatoslav Ryhel
2024-04-19 16:26 ` Thierry Reding
2024-04-19 16:34 ` Thierry Reding [this message]
2024-04-19 17:16 ` Svyatoslav Ryhel
2024-01-23 17:16 ` [PATCH v6 02/18] video: tegra20: dc: fix image shift on rotated panels Svyatoslav Ryhel
2024-04-19 16:33 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 03/18] video: tegra20: consolidate DC header Svyatoslav Ryhel
2024-04-19 15:56 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 04/18] video: tegra20: dc: pass DC id to internal devices Svyatoslav Ryhel
2024-04-19 16:38 ` Thierry Reding
2024-04-19 16:44 ` Svyatoslav Ryhel
2024-04-19 16:58 ` Thierry Reding
2024-04-19 17:02 ` Svyatoslav Ryhel
2024-01-23 17:16 ` [PATCH v6 05/18] video: tegra20: dc: add PLLD2 parent support Svyatoslav Ryhel
2024-04-19 16:50 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 06/18] video: tegra20: dc: add reset support Svyatoslav Ryhel
2024-04-19 16:05 ` Thierry Reding
2024-04-19 16:37 ` Svyatoslav Ryhel
2024-04-19 16:46 ` Thierry Reding
2024-04-19 16:53 ` Svyatoslav Ryhel
2024-01-23 17:16 ` [PATCH v6 07/18] video: tegra20: dc: add powergate Svyatoslav Ryhel
2024-04-19 16:55 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 08/18] video: tegra20: dc: configure behavior if PLLD/D2 is used Svyatoslav Ryhel
2024-04-19 16:48 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 09/18] video: tegra20: dc: fix printing of framebuffer address Svyatoslav Ryhel
2024-04-19 17:03 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 10/18] video: tegra20: dc: enable backlight after DC is configured Svyatoslav Ryhel
2024-04-19 16:35 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 11/18] video: tegra20: dc: clean framebuffer memory block Svyatoslav Ryhel
2024-04-19 16:54 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 12/18] video: tegra20: dc: parameterize V- and H-sync polarities Svyatoslav Ryhel
2024-04-19 17:00 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 13/18] video: tegra20: add MIPI calibration driver Svyatoslav Ryhel
2024-04-19 16:10 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 14/18] video: tegra20: dsi: add T114 support Svyatoslav Ryhel
2024-04-19 16:29 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 15/18] video: tegra20: dsi: add reset support Svyatoslav Ryhel
2024-04-19 16:52 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 16/18] video: tegra20: dsi: remove pre-configuration Svyatoslav Ryhel
2024-04-19 16:41 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 17/18] video: tegra20: dsi: set correct fifo depth Svyatoslav Ryhel
2024-04-19 16:30 ` Thierry Reding
2024-01-23 17:16 ` [PATCH v6 18/18] video: tegra20: dsi: use set_backlight for backlight only Svyatoslav Ryhel
2024-04-19 16:00 ` Thierry Reding
2024-04-19 11:30 ` [PATCH v6 00/18] Add T114 video support Svyatoslav Ryhel
2024-04-20 23:02 ` Anatolij Gustschin
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