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[2003:e4:1f16:2000:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id m11-20020a1709060d8b00b00a525a18f748sm2396708eji.165.2024.04.19.09.58.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Apr 2024 09:58:04 -0700 (PDT) Content-Type: multipart/signed; boundary=0e8ae7b8ac1ecae429f5138b6498fcc0f0e8758c87acbf78460563aaf1d2; micalg=pgp-sha256; protocol="application/pgp-signature" Mime-Version: 1.0 Date: Fri, 19 Apr 2024 18:58:04 +0200 Message-Id: Subject: Re: [PATCH v6 04/18] video: tegra20: dc: pass DC id to internal devices From: "Thierry Reding" To: "Svyatoslav Ryhel" Cc: "Thierry Reding" , "Anatolij Gustschin" , "Simon Glass" , X-Mailer: aerc 0.16.0-1-0-g560d6168f0ed-dirty References: <20240123171633.246057-1-clamor95@gmail.com> <20240123171633.246057-5-clamor95@gmail.com> In-Reply-To: X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean --0e8ae7b8ac1ecae429f5138b6498fcc0f0e8758c87acbf78460563aaf1d2 Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 On Fri Apr 19, 2024 at 6:44 PM CEST, Svyatoslav Ryhel wrote: > =D0=BF=D1=82, 19 =D0=BA=D0=B2=D1=96=D1=82. 2024=E2=80=AF=D1=80. =D0=BE 19= :38 Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5: > > > > On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > > > Tegra SoC has 2 independent display controllers called DC_A and > > > DC_B, they are handled differently by internal video devices like > > > DSI and HDMI controllers so it is important for last to know > > > which display controller is used to properly set up registers. > > > To achieve this, a pipe field was added to pdata to pass display > > > controller id to internal Tegra SoC devices. > > > > > > Tested-by: Agneli # Toshiba AC100 T20 > > > Tested-by: Robert Eckelmann # ASUS TF101 > > > Tested-by: Andreas Westman Dorcsak # ASUS Grouper = E1565 > > > Tested-by: Ion Agorria # HTC One X > > > Tested-by: Svyatoslav Ryhel # Nvidia Tegratab T1= 14 > > > Signed-off-by: Svyatoslav Ryhel > > > --- > > > drivers/video/tegra20/tegra-dc.c | 6 ++++++ > > > drivers/video/tegra20/tegra-dc.h | 3 +++ > > > 2 files changed, 9 insertions(+) > > > > > > diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20= /tegra-dc.c > > > index 5d8874f323..0e94e665ef 100644 > > > --- a/drivers/video/tegra20/tegra-dc.c > > > +++ b/drivers/video/tegra20/tegra-dc.c > > > @@ -45,6 +45,7 @@ struct tegra_lcd_priv { > > > unsigned pixel_clock; /* Pixel clock in Hz */ > > > int dc_clk[2]; /* Contains clk and its parent = */ > > > bool rotation; /* 180 degree panel turn */ > > > + bool pipe; /* DC controller: 0 for A, 1 fo= r B */ > > > > Bool is a poor choice, even if there's only two of them. This is a > > proper index, so it should be some sort of integer. > > > > Also, the device tree bindings for the display controller specify a > > "nvidia,head" property that can be used to identify these. If you add > > that to the U-Boot DT you can avoid looking up by name to map this > > value. > > > > Thanks for pointing to this property. May we apply this patch set as is > since it is well tested and confirmed to work and I will prepare a follow > up patches to adjust device tree relations? Would what be ok? Well, there's a few other things that I think should be addressed, but if you'd like to keep this one patch as-is and clean this up later, I guess that's fine. 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