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[34.66.65.137]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-502048c6ceesm186583173.47.2025.06.26.14.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jun 2025 14:56:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A0DB360754; Thu, 26 Jun 2025 21:56:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marliere.net; s=dkim; t=1750975004; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=SC20LiWWtz5KUGCUi3XhzR02YMG6updQi+P8j0cV62w=; b=mv0fhGa94wO/UQhp4OdAkxH5b89ZD3v2PPYpDJBy3JwJFOGIwx5TvAQDZYac5loeko4T/p ILDcAD2roEiXwGheobmYMFoznfRa8F4kO06gCR0Aj5fgrYyR7Kw8LifCplki86bMNgBnT3 JrPCFSpXzxwP985C5bA7Z5kTtAXd9ISqLXb5+U1KVKIpEuYVlc0B0gLDwm8xLV6iHkG8+U bzfnP4hun+NzhmNwnd9M6ZzZOFHXdmIskJBn3DHEjGzT3DX/3Lc6yXPMdGNAS4TWFvlzl7 UB0CLdjJfZIRJewMiMBLc0tOwrM2rL8Ht3pf2LAVc38jenA7+DXKtuIKCcTNkQ== From: =?utf-8?B?UmljYXJkbyBCLiBNYXJsacOocmU=?= Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 26 Jun 2025 18:56:34 -0300 Message-Id: Subject: Re: [PATCH 0/5] Convert Lichee Pi 4A to use S-Mode proper U-Boot Cc: , "Han Gao" , "Han Gao" , "U-Boot" To: "Yao Zi" , "Rick Chen" , "Leo" , "Tom Rini" , "Wei Fu" , "Yixun Lan" , "Ilias Apalodimas" , "Maksim Kiselev" , "Jaehoon Chung" , "Jerome Forissier" , "Sughosh Ganu" X-Mailer: aerc 0.20.1-80-g1fe8ed687c05-dirty References: <20250530094851.57198-1-ziyao@disroot.org> In-Reply-To: <20250530094851.57198-1-ziyao@disroot.org> X-Last-TLS-Session-Version: TLSv1.3 X-Mailman-Approved-At: Fri, 27 Jun 2025 00:16:19 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Fri May 30, 2025 at 6:48 AM -03, Yao Zi wrote: > RISC-V software usually expects that HARTs are running under S mode when > leaving the firmware, for example, the UEFI specification explicitly > states requirements for S mode. > > This series separates M-mode-only code for TH1520 port out, and > configures binman to pack the OpenSBI firmware to initialize the S-mode > environment. Then S-mode proper U-Boot is enabled on our Lichee Pi 4A > port. > > Note that booting on Lichee Pi 4A is broken between PATCH 3 and 4, > affecting bisectability. Considering TH1520 port is still in an early > stage and separating the changes make the commit cleaner, I personally > consider it's acceptable. > > Yao Zi (5): > riscv: cpu: th1520: Build spl.c for SPL only > riscv: cpu: th1520: Support cache enabling/disabling in M mode only > riscv: dts: th1520: Prepare binman configuration for loading OpenSBI > board: thead: licheepi4a: Run proper U-Boot in S-Mode > doc: thead: lpi4a: Update for S-Mode proper U-Boot support > > arch/riscv/cpu/th1520/Makefile | 2 +- > arch/riscv/cpu/th1520/cache.c | 2 + > arch/riscv/dts/thead-th1520-binman.dtsi | 32 +++++- > configs/th1520_lpi4a_defconfig | 1 + > doc/board/thead/lpi4a.rst | 125 +++++++----------------- > 5 files changed, 68 insertions(+), 94 deletions(-) I also tested with OpenSBI 1.6 on a Lichee Pi 4A 8GB. Tested-by: Ricardo B. Marli=C3=A8re