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Thu, 30 Oct 2025 10:25:59 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE215.ent.ti.com (157.170.170.118) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Thu, 30 Oct 2025 10:25:59 -0500 Received: from localhost (dhcp-172-24-233-105.dhcp.ti.com [172.24.233.105]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59UFPwNe2404270; Thu, 30 Oct 2025 10:25:59 -0500 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Date: Thu, 30 Oct 2025 20:55:58 +0530 Message-ID: To: Andrew Davis , Anshul Dalal CC: , , , , , , , Subject: Re: [PATCH v9 3/8] mach-k3: common: enable falcon mode from R5 SPL From: Anshul Dalal X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20251030051937.3659010-1-anshuld@ti.com> <20251030051937.3659010-4-anshuld@ti.com> In-Reply-To: X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E61:EE_|IA3PR10MB8089:EE_ X-MS-Office365-Filtering-Correlation-Id: 499461d5-7551-4d42-334c-08de17c8a385 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:lewvzet200.ext.ti.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(1800799024)(34020700016)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2025 15:26:03.6855 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 499461d5-7551-4d42-334c-08de17c8a385 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7; Ip=[198.47.23.194]; Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA3PR10MB8089 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Thu Oct 30, 2025 at 7:16 PM IST, Andrew Davis wrote: > On 10/30/25 12:19 AM, Anshul Dalal wrote: >> We use the spl_board_prepare_for_boot hook to call k3_r5_falcon_prep >> which is ran after tispl is loaded but before jump_to_image. >>=20 >> In k3_r5_falcon_prep, we find the boot media and load the kernel FIT >> just as standard secure falcon mode (since spl_start_uboot returns 0 >> now). Once the kernel and args are loaded. >>=20 >> Now when the flow goes to jump_to_image, we do the regular pre-jump >> procedure and jump to TFA which jumps to the kernel directly since we >> have already loaded the kernel and dtb at their respective addresses >> (PRELOADED_BL33_BASE and K3_HW_CONFIG_BASE). >>=20 >> Signed-off-by: Anshul Dalal >> --- >> arch/arm/mach-k3/common.c | 8 +++++++ >> arch/arm/mach-k3/common.h | 4 ++++ >> arch/arm/mach-k3/r5/common.c | 45 ++++++++++++++++++++++++++++++++++++ >> 3 files changed, 57 insertions(+) >>=20 >> diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c >> index 04a0f232d84..c446d1c47fd 100644 >> --- a/arch/arm/mach-k3/common.c >> +++ b/arch/arm/mach-k3/common.c >> @@ -360,6 +360,14 @@ void spl_perform_arch_fixups(struct spl_image_info = *spl_image) >> =20 >> void spl_board_prepare_for_boot(void) >> { >> +#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) && !IS_ENABLED(CONFIG_ARM64) >> + int ret; >> + >> + ret =3D k3_r5_falcon_prep(); >> + if (ret) >> + panic("%s: Failed to boot in falcon mode: %d\n", __func__, ret); >> +#endif /* falcon mode on R5 SPL */ >> + >> #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)= ) >> dcache_disable(); >> #endif >> diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h >> index 52d3faaab5c..5807d358464 100644 >> --- a/arch/arm/mach-k3/common.h >> +++ b/arch/arm/mach-k3/common.h >> @@ -52,6 +52,10 @@ void do_board_detect(void); >> void ti_secure_image_check_binary(void **p_image, size_t *p_size); >> int shutdown_mcu_r5_core1(void); >> =20 >> +#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) && !IS_ENABLED(CONFIG_ARM64) >> +int k3_r5_falcon_bootmode(void); >> +#endif >> + >> #if (IS_ENABLED(CONFIG_K3_QOS)) >> void setup_qos(void); >> #else >> diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c >> index 6269b33f66b..439dd92ef54 100644 >> --- a/arch/arm/mach-k3/r5/common.c >> +++ b/arch/arm/mach-k3/r5/common.c >> @@ -376,3 +376,48 @@ void board_fit_image_post_process(const void *fit, = int node, void **p_image, >> } >> } >> #endif >> + >> +#ifdef CONFIG_SPL_OS_BOOT_SECURE >> + >> +static bool tifalcon_loaded; > > Not strictly needed as statics will default to 0, assigning false > here makes it more clear what the starting value should be, > > static bool tifalcon_loaded =3D false; > >> + >> +int spl_start_uboot(void) >> +{ >> + /* If tifalcon.bin is not loaded, proceed to regular boot */ >> + if (!tifalcon_loaded) >> + return 1; >> + >> + /* Boot to linux on R5 SPL with tifalcon.bin loaded */ >> + return 0; > > Extra indent tab here. > >> +} >> + >> +int k3_r5_falcon_prep(void) >> +{ >> + struct spl_image_loader *loader, *drv; >> + struct spl_image_info kernel_image; >> + struct spl_boot_device bootdev; >> + int ret =3D -ENXIO, n_ents; >> + >> + tifalcon_loaded =3D true; > > Should this be set down after we make sure loading doesn't fail? > That wouldn't work actually, tifalcon_loaded is used to detect if tifalcon.bin has been loaded or not. We then in-turn use this information in our two step boot process to decide whether or not to do falcon boot. The call to load_image below will internally calls spl_start_uboot to check for falcon mode status, which will return 0 now allowing us to load fitImage. So, the overall boot flow looks as follows: board_init_r |-> boot_from_devices | +-> load_image (we load tifalcon.bin here since spl_start_uboot return= s 1) | +-> spl_prepare_for_boot | +-> k3_falcon_prep | +-> load_image (we load fitImage here since spl_start_uboot return= s 0 now) | +-> jump_to_image >> + memset(&kernel_image, '\0', sizeof(kernel_image)); >> + drv =3D ll_entry_start(struct spl_image_loader, spl_image_loader); >> + n_ents =3D ll_entry_count(struct spl_image_loader, spl_image_loader); >> + bootdev.boot_device =3D spl_boot_device(); >> + >> + for (loader =3D drv; loader !=3D drv + n_ents; loader++) { >> + if (bootdev.boot_device !=3D loader->boot_device) >> + continue; >> + if (loader) { > > If loader is NULL, the if above containing loader->boot_device would have > already null pointer deref crashed. You might want to move this check up > into the if check above. You're right, this needs to be fixed. I was following a similar structure to boot_from_devices (common/spl/spl.c) which also seems to have the same issue. Regards, Anshul > > Andrew > >> + printf("Loading falcon payload from %s\n", >> + spl_loader_name(loader)); >> + ret =3D loader->load_image(&kernel_image, &bootdev); >> + if (ret) >> + continue; >> + >> + return 0; >> + } >> + } >> + >> + return ret; >> +} >> +#endif