From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 57494CFC28F for ; Fri, 21 Nov 2025 16:08:56 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8950C8394E; Fri, 21 Nov 2025 17:08:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="sRMn03q3"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0A21983984; Fri, 21 Nov 2025 17:08:54 +0100 (CET) Received: from sea.source.kernel.org (sea.source.kernel.org [IPv6:2600:3c0a:e001:78e:0:1991:8:25]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4B77B836F0 for ; Fri, 21 Nov 2025 17:08:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=mwalle@kernel.org Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 7296443B6C; Fri, 21 Nov 2025 16:08:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AED9AC19421; Fri, 21 Nov 2025 16:08:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763741329; bh=Si/3BHhR2XsCtSJy/qBUFgTHT0rLWTh7e8P8eIFha+c=; h=Date:Cc:From:To:Subject:References:In-Reply-To:From; b=sRMn03q3Fn3aPUzMK1ufQ756gCmU2NoRnJ4p6KZ0lyDt5hqrOAcv6VlGV/6vHs+O2 652HxKhxdJKBCG0bX2DZ3eFCTrhZpOZmLG47Kvw/GTkmESYfKlxHdeC8jlGEI9UwM/ nj/GpZpQxOHwRSe7UBz7/UF7bnP0UToOppBCFTNP9CCJQ5OXMW7IsS1OuPgSCr2lLu mb66n1aQolpWQ+S9R9fBQSJZH+Xv/qc7dFA3CpNM2apyJBrfn3KgWhpanlALm3pY3I 8Js63ZBFFK65L9fmcTKYnEsPq2ZrD1px+kO3o+2a2GFW2yO4lG7B9nA1GKdkiZdVV1 ToJ61Uf7IROLA== Mime-Version: 1.0 Content-Type: multipart/signed; boundary=8446655d6e531e4ebb7d1ef665261abf901f8211fc95d4881c1ee5fe78ce; micalg=pgp-sha384; protocol="application/pgp-signature" Date: Fri, 21 Nov 2025 17:08:39 +0100 Message-Id: Cc: From: "Michael Walle" To: "Chintan Vankar" , "Richard Genoud" , "Sam Protsenko" , "Santhosh Kumar K" , "Jonathan Humphreys" , "Mattijs Korpershoek" , "Ilias Apalodimas" , "Bhavya Kapoor" , "Parth Pancholi" , "Andreas Dannenberg" , "Moteen Shah" , "Beleswar Padhi" , "Anshul Dalal" , "Sughosh Ganu" , "Neha Malcom Francis" , "Prasanth Babu Mantena" , "Wadim Egorov" , "Simon Glass" , "Alexander Sverdlin" , "Siddharth Vadapalli" , "Kishon Vijay Abraham I" , "Ramon Fried" , "Joe Hershberger" , "Jayesh Choudhary" , "Vaishnav Achath" , "Bryan Brattlof" , "Vignesh Raghavendra" , "Tom Rini" Subject: Re: [PATCH v4 14/21] arm: mach-k3: j722s: Update SoC autogenerated data to enable Ethernet boot X-Mailer: aerc 0.20.0 References: <20250731075956.605474-1-c-vankar@ti.com> <20250731075956.605474-15-c-vankar@ti.com> In-Reply-To: <20250731075956.605474-15-c-vankar@ti.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean --8446655d6e531e4ebb7d1ef665261abf901f8211fc95d4881c1ee5fe78ce Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Hi, On Thu Jul 31, 2025 at 9:59 AM CEST, Chintan Vankar wrote: > Update dev-data and clk-data to include CPSW device which is required to > enable Ethernet boot. > This breaks eMMC boot on our board: U-Boot SPL 2026.01-rc2-00054-g32334645579c (Nov 21 2025 - 15:49:13 +0100) SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.3--v11.01.03 (Fancy Rat)') SPL initial stack usage: 17048 bytes ti_power_domain_of_xlate: invalid dev-id: 57 ti_power_domain_of_xlate: invalid dev-id: 57 Trying to boot from eMMC (boot0) ti_power_domain_of_xlate: invalid dev-id: 57 ti_power_domain_of_xlate: invalid dev-id: 57 spl: could not initialize mmc. error: -2 Error: -2 SPL: Unsupported Boot Device! SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Not sure how this file was autogenerated but it removes ID 57.. see more below. Reverting this patch will make (at least) the r5 SPL work again. There seems to be more issues with the u-boot proper, but I haven't investigated that yet. > Signed-off-by: Chintan Vankar > --- > > Link to v3: > https://lore.kernel.org/u-boot/20250225114903.2080616-13-c-vankar@ti.com/ > > Changes from v3 to v4: > - No changes. > > arch/arm/mach-k3/r5/j722s/clk-data.c | 50 ++++++++++++++++++++++------ > arch/arm/mach-k3/r5/j722s/dev-data.c | 34 +++++++++---------- > 2 files changed, 56 insertions(+), 28 deletions(-) > > diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j= 722s/clk-data.c > index b4f27af333d..238d57d0aa0 100644 > --- a/arch/arm/mach-k3/r5/j722s/clk-data.c > +++ b/arch/arm/mach-k3/r5/j722s/clk-data.c > @@ -5,7 +5,7 @@ > * This file is auto generated. Please do not hand edit and report any i= ssues > * to Bryan Brattlof . > * > - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.co= m/ > + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.= ti.com/ > */ > =20 > #include > @@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = =3D { > "hsdiv4_16fft_main_2_hsdivout1_clk", > }; > =20 > -static const char * const main_emmcsd0_refclk_sel_out0_parents[] =3D { > - "postdiv4_16ff_main_0_hsdivout5_clk", > - "hsdiv4_16fft_main_2_hsdivout2_clk", > +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] =3D = { > + "postdiv4_16ff_main_2_hsdivout5_clk", > + "postdiv4_16ff_main_0_hsdivout6_clk", > + "board_0_cp_gemac_cpts0_rft_clk_out", > + NULL, > + "board_0_mcu_ext_refclk0_out", > + "board_0_ext_refclk1_out", > + NULL, > + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", > }; > =20 > static const char * const main_emmcsd1_refclk_sel_out0_parents[] =3D { > @@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_pare= nts[] =3D { > "board_0_cp_gemac_cpts0_rft_clk_out", > "hsdiv4_16fft_main_1_hsdivout3_clk", > "postdiv4_16ff_main_2_hsdivout6_clk", > - NULL, > - NULL, > + "cpsw_3guss_am67_main_0_cpts_genf0", > + "cpsw_3guss_am67_main_0_cpts_genf1", > NULL, > NULL, > NULL, > @@ -143,7 +149,12 @@ static const struct clk_data clk_list[] =3D { > CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), > CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), > CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), > + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), > + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), > CLK_FIXED_RATE("board_0_tck_out", 0, 0), > + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0), > + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0), > + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0), > CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), > CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), > CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), > @@ -194,7 +205,7 @@ static const struct clk_data clk_list[] =3D { > CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ct= rl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), > CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_= wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), > CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0,= 1, 0), > - CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_pa= rents, 2, 0x108160, 0, 1, 0), > + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_o= ut0_parents, 8, 0x108140, 0, 3, 0), > CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_pa= rents, 2, 0x108168, 0, 1, 0), > CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x4300= 8030, 0, 3, 0), > CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parent= s, 2, 0x108500, 0, 1, 0), > @@ -209,6 +220,24 @@ static const struct clk_data clk_list[] =3D { > }; > =20 > static const struct dev_clk soc_dev_clk_data[] =3D { > + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), > + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), > + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), > + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), > + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), > + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), > + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), > + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), > + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"), > + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"), > DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), > DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), > DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), > @@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] =3D { > DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), > DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), > DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), > - DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), > - DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), > - DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), > - DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), > + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), > + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), > DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), > DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), > DEV_CLK(58, 2, "board_0_mmc1_clk_out"), > @@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] =3D { > DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), > DEV_CLK(157, 74, "mshsi2c_main_0_porscl"), > DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), > + DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"), > DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), > DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), > DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), > diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j= 722s/dev-data.c > index 59176c98999..d6832266884 100644 > --- a/arch/arm/mach-k3/r5/j722s/dev-data.c > +++ b/arch/arm/mach-k3/r5/j722s/dev-data.c > @@ -5,7 +5,7 @@ > * This file is auto generated. Please do not hand edit and report any i= ssues > * to Bryan Brattlof . > * > - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.co= m/ > + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.= ti.com/ > */ > =20 > #include "k3-dev.h" > @@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] =3D { > =20 > static struct ti_lpsc soc_lpsc_list[] =3D { > [0] =3D PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), > - [1] =3D PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 5]), > - [2] =3D PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 5]), > - [3] =3D PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 7]), > - [4] =3D PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 7]), > - [5] =3D PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 7]), > - [6] =3D PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 7]), > - [7] =3D PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 7]), > - [8] =3D PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[= 7]), > + [1] =3D PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 4]), > + [2] =3D PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 4]), > + [3] =3D PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 6]), > + [4] =3D PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 6]), > + [5] =3D PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 6]), > + [6] =3D PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 6]), > + [7] =3D PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[= 6]), > + [8] =3D PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[= 6]), > [9] =3D PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[= 8]), > - [10] =3D PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list= [7]), > + [10] =3D PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list= [6]), > [11] =3D PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list= [10]), > [12] =3D PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list= [11]), > }; > @@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] =3D { > PSC_DEV(61, &soc_lpsc_list[0]), > PSC_DEV(178, &soc_lpsc_list[1]), > PSC_DEV(179, &soc_lpsc_list[2]), > - PSC_DEV(57, &soc_lpsc_list[3]), This seems to be relevant. -michael > - PSC_DEV(58, &soc_lpsc_list[4]), > - PSC_DEV(161, &soc_lpsc_list[5]), > - PSC_DEV(75, &soc_lpsc_list[6]), > - PSC_DEV(36, &soc_lpsc_list[7]), > - PSC_DEV(102, &soc_lpsc_list[7]), > - PSC_DEV(146, &soc_lpsc_list[7]), > + PSC_DEV(58, &soc_lpsc_list[3]), > + PSC_DEV(161, &soc_lpsc_list[4]), > + PSC_DEV(75, &soc_lpsc_list[5]), > + PSC_DEV(36, &soc_lpsc_list[6]), > + PSC_DEV(102, &soc_lpsc_list[6]), > + PSC_DEV(146, &soc_lpsc_list[6]), > + PSC_DEV(13, &soc_lpsc_list[7]), > PSC_DEV(166, &soc_lpsc_list[8]), > PSC_DEV(135, &soc_lpsc_list[9]), > PSC_DEV(170, &soc_lpsc_list[10]), --8446655d6e531e4ebb7d1ef665261abf901f8211fc95d4881c1ee5fe78ce Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iKgEABMJADAWIQTIVZIcOo5wfU/AngkSJzzuPgIf+AUCaSCOiBIcbXdhbGxlQGtl cm5lbC5vcmcACgkQEic87j4CH/jOGwF/UZZmQtWq16XbsRA0gghi3V4WqvKQ9GLr FEi5a2Osrn93MacFswUnOe/eJwmD1KahAYC/Gy2JS+leYBwecAx6F+KMpGOMcfeg vz7gIRg6ykMvWunggUip14KMzhMYsmmqMNY= =wqoo -----END PGP SIGNATURE----- --8446655d6e531e4ebb7d1ef665261abf901f8211fc95d4881c1ee5fe78ce--