[PATCH v4 10/21] arm: mach-k3: am62p: Update SoC auto-gen data to enable Ethernet boot

Chintan Vankar
2025-07-31T08:20:42Z

From: Andreas Dannenberg <dannenberg@ti.com>

Update dev-data and clk-data to enable Ethernet boot using CPSW on
SK-AM62P-LP.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-9-c-vankar@ti.com/

Changes from v3 to v4:
- No changes.

arch/arm/mach-k3/r5/am62px/clk-data.c | 44 +++++++++++++++++++++++++--
arch/arm/mach-k3/r5/am62px/dev-data.c | 24 ++++++++-------
2 files changed, 54 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c
index bc62d1d0d08..b552a2be74d 100644
--- a/arch/arm/mach-k3/r5/am62px/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62px/clk-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
- * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/

#include <linux/clk-provider.h>
@@ -62,6 +62,17 @@ static const char * const clkout0_ctrl_out0_parents[] = {
"hsdiv4_16fft_main_2_hsdivout1_clk10",
};

+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
"postdiv4_16ff_main_0_hsdivout5_clk",
"hsdiv4_16fft_main_2_hsdivout2_clk",
@@ -99,8 +110,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
"board_0_cp_gemac_cpts0_rft_clk_out",
"hsdiv4_16fft_main_1_hsdivout3_clk",
"postdiv4_16ff_main_2_hsdivout6_clk",
- NULL,
- NULL,
+ "cpsw_3guss_am67_main_0_cpts_genf0",
+ "cpsw_3guss_am67_main_0_cpts_genf1",
NULL,
NULL,
NULL,
@@ -148,7 +159,12 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -201,6 +217,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+ CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
@@ -216,6 +233,24 @@ static const struct clk_data clk_list[] = {
};

static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+ DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
+ DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -240,6 +275,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
+ DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
+ DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
@@ -286,6 +323,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 54, "mshsi2c_main_0_porscl"),
DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+ DEV_CLK(157, 96, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
diff --git a/arch/arm/mach-k3/r5/am62px/dev-data.c b/arch/arm/mach-k3/r5/am62px/dev-data.c
index 3cc211ea202..63e6beb4d57 100644
--- a/arch/arm/mach-k3/r5/am62px/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62px/dev-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
- * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/

#include "k3-dev.h"
@@ -31,11 +31,12 @@ static struct ti_lpsc soc_lpsc_list[] = {
[6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
[7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
[8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
- [9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
- [10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]),
- [11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
- [12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
- [13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+ [9] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
+ [10] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
+ [11] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[10]),
+ [12] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
+ [13] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+ [14] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[13]),
};

static struct ti_dev soc_dev_list[] = {
@@ -52,11 +53,12 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(36, &soc_lpsc_list[8]),
PSC_DEV(102, &soc_lpsc_list[8]),
PSC_DEV(146, &soc_lpsc_list[8]),
- PSC_DEV(166, &soc_lpsc_list[9]),
- PSC_DEV(135, &soc_lpsc_list[10]),
- PSC_DEV(170, &soc_lpsc_list[11]),
- PSC_DEV(177, &soc_lpsc_list[12]),
- PSC_DEV(55, &soc_lpsc_list[13]),
+ PSC_DEV(13, &soc_lpsc_list[9]),
+ PSC_DEV(166, &soc_lpsc_list[10]),
+ PSC_DEV(135, &soc_lpsc_list[11]),
+ PSC_DEV(170, &soc_lpsc_list[12]),
+ PSC_DEV(177, &soc_lpsc_list[13]),
+ PSC_DEV(55, &soc_lpsc_list[14]),
};

const struct ti_k3_pd_platdata am62px_pd_platdata = {
--
2.34.1