* Re: [PATCH] arm: armv8: Flush TLB before enabling MMU
2026-01-10 19:56 [PATCH] arm: armv8: Flush TLB before enabling MMU Mark Kettenis
@ 2026-01-12 4:32 ` Anshul Dalal
2026-01-20 11:01 ` Ilias Apalodimas
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Anshul Dalal @ 2026-01-12 4:32 UTC (permalink / raw)
To: Mark Kettenis, u-boot
Cc: trini, ilias.apalodimas, anshuld, d-gole, casey.connolly
On Sun Jan 11, 2026 at 1:26 AM IST, Mark Kettenis wrote:
> Commit 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on
> dcache_enable") broke Apple Silicon machines in certain scenarios.
> If the MMU is currently not enabled we need to flush the TLB
> before we enable it to prevent stale TLB entries from becoming
> active again. So move the __asm_invalidate_tlb_all() back
> immediately before the mmu_setup() call.
>
> Fixes: 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on dcache_enable")
> Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
> ---
> arch/arm/cpu/armv8/cache_v8.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index 0309da6d397..39479df7b21 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -878,15 +878,16 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
> void dcache_enable(void)
> {
> /* The data cache is not active unless the mmu is enabled */
> - if (!mmu_status())
> + if (!mmu_status()) {
> + __asm_invalidate_tlb_all();
> mmu_setup();
So, if I understand correctly the problem is that the TLB is enabled by
mmu_setup which happened before we invalidated the existing TLB entries?
> + }
>
> /* Set up page tables only once (it is done also by mmu_setup()) */
> if (!gd->arch.tlb_fillptr)
> setup_all_pgtables();
>
> invalidate_dcache_all();
> - __asm_invalidate_tlb_all();
> set_sctlr(get_sctlr() | CR_C);
> }
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] arm: armv8: Flush TLB before enabling MMU
2026-01-10 19:56 [PATCH] arm: armv8: Flush TLB before enabling MMU Mark Kettenis
2026-01-12 4:32 ` Anshul Dalal
@ 2026-01-20 11:01 ` Ilias Apalodimas
2026-02-23 21:23 ` Mark Kettenis
2026-02-24 20:02 ` Tom Rini
3 siblings, 0 replies; 6+ messages in thread
From: Ilias Apalodimas @ 2026-01-20 11:01 UTC (permalink / raw)
To: Mark Kettenis; +Cc: u-boot, trini, anshuld, d-gole, casey.connolly
Hi Mark,
On Sat, 10 Jan 2026 at 21:56, Mark Kettenis <kettenis@openbsd.org> wrote:
>
> Commit 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on
> dcache_enable") broke Apple Silicon machines in certain scenarios.
> If the MMU is currently not enabled we need to flush the TLB
> before we enable it to prevent stale TLB entries from becoming
> active again. So move the __asm_invalidate_tlb_all() back
> immediately before the mmu_setup() call.
>
> Fixes: 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on dcache_enable")
> Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
> ---
Should we keep the check here or mayber move it in mmu_setup()?
Thanks
/Ilias
> arch/arm/cpu/armv8/cache_v8.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index 0309da6d397..39479df7b21 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -878,15 +878,16 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
> void dcache_enable(void)
> {
> /* The data cache is not active unless the mmu is enabled */
> - if (!mmu_status())
> + if (!mmu_status()) {
> + __asm_invalidate_tlb_all();
> mmu_setup();
> + }
>
> /* Set up page tables only once (it is done also by mmu_setup()) */
> if (!gd->arch.tlb_fillptr)
> setup_all_pgtables();
>
> invalidate_dcache_all();
> - __asm_invalidate_tlb_all();
> set_sctlr(get_sctlr() | CR_C);
> }
>
> --
> 2.52.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] arm: armv8: Flush TLB before enabling MMU
2026-01-10 19:56 [PATCH] arm: armv8: Flush TLB before enabling MMU Mark Kettenis
2026-01-12 4:32 ` Anshul Dalal
2026-01-20 11:01 ` Ilias Apalodimas
@ 2026-02-23 21:23 ` Mark Kettenis
2026-02-24 10:18 ` Ilias Apalodimas
2026-02-24 20:02 ` Tom Rini
3 siblings, 1 reply; 6+ messages in thread
From: Mark Kettenis @ 2026-02-23 21:23 UTC (permalink / raw)
To: Mark Kettenis
Cc: u-boot, trini, ilias.apalodimas, anshuld, d-gole, casey.connolly,
kettenis
> Hi Mark,
Hi Ilias,
Sorry for the late reply. I was a bit busy the last weeks...
> On Sat, 10 Jan 2026 at 21:56, Mark Kettenis <kettenis@openbsd.org> wrote:
> >
> > Commit 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on
> > dcache_enable") broke Apple Silicon machines in certain scenarios.
> > If the MMU is currently not enabled we need to flush the TLB
> > before we enable it to prevent stale TLB entries from becoming
> > active again. So move the __asm_invalidate_tlb_all() back
> > immediately before the mmu_setup() call.
> >
> > Fixes: 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on dcache_enable")
> > Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
> > ---
>
> Should we keep the check here or mayber move it in mmu_setup()?
It would make sense to move it to mmu_setup(), but I went for a
partial revert as there is an alternative implementation of
mmu_setup() in cpu/armv8/fsl-layerscape/cpu.c and I couldn't test that
code.
Hope this can still make the next release.
> Thanks
> /Ilias
>
> > arch/arm/cpu/armv8/cache_v8.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
>
> > diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> > index 0309da6d397..39479df7b21 100644
> > --- a/arch/arm/cpu/armv8/cache_v8.c
> > +++ b/arch/arm/cpu/armv8/cache_v8.c
> > @@ -878,15 +878,16 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
> > void dcache_enable(void)
> > {
> > /* The data cache is not active unless the mmu is enabled */
> > - if (!mmu_status())
> > + if (!mmu_status()) {
> > + __asm_invalidate_tlb_all();
> > mmu_setup();
> > + }
> >
> > /* Set up page tables only once (it is done also by mmu_setup()) */
> > if (!gd->arch.tlb_fillptr)
> > setup_all_pgtables();
> >
> > invalidate_dcache_all();
> > - __asm_invalidate_tlb_all();
> > set_sctlr(get_sctlr() | CR_C);
> > }
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] arm: armv8: Flush TLB before enabling MMU
2026-02-23 21:23 ` Mark Kettenis
@ 2026-02-24 10:18 ` Ilias Apalodimas
0 siblings, 0 replies; 6+ messages in thread
From: Ilias Apalodimas @ 2026-02-24 10:18 UTC (permalink / raw)
To: Mark Kettenis
Cc: Mark Kettenis, u-boot, trini, anshuld, d-gole, casey.connolly
On Mon, 23 Feb 2026 at 23:23, Mark Kettenis <mark.kettenis@xs4all.nl> wrote:
>
> > Hi Mark,
>
> Hi Ilias,
>
> Sorry for the late reply. I was a bit busy the last weeks...
>
> > On Sat, 10 Jan 2026 at 21:56, Mark Kettenis <kettenis@openbsd.org> wrote:
> > >
> > > Commit 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on
> > > dcache_enable") broke Apple Silicon machines in certain scenarios.
> > > If the MMU is currently not enabled we need to flush the TLB
> > > before we enable it to prevent stale TLB entries from becoming
> > > active again. So move the __asm_invalidate_tlb_all() back
> > > immediately before the mmu_setup() call.
> > >
> > > Fixes: 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on dcache_enable")
> > > Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
> > > ---
> >
> > Should we keep the check here or mayber move it in mmu_setup()?
>
> It would make sense to move it to mmu_setup(), but I went for a
> partial revert as there is an alternative implementation of
> mmu_setup() in cpu/armv8/fsl-layerscape/cpu.c and I couldn't test that
> code.
>
> Hope this can still make the next release.
Ok that's unfortunate. Let's get it in now since it's a fix
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
>
> > Thanks
> > /Ilias
> >
> > > arch/arm/cpu/armv8/cache_v8.c | 5 +++--
> > > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > > diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> > > index 0309da6d397..39479df7b21 100644
> > > --- a/arch/arm/cpu/armv8/cache_v8.c
> > > +++ b/arch/arm/cpu/armv8/cache_v8.c
> > > @@ -878,15 +878,16 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
> > > void dcache_enable(void)
> > > {
> > > /* The data cache is not active unless the mmu is enabled */
> > > - if (!mmu_status())
> > > + if (!mmu_status()) {
> > > + __asm_invalidate_tlb_all();
> > > mmu_setup();
> > > + }
> > >
> > > /* Set up page tables only once (it is done also by mmu_setup()) */
> > > if (!gd->arch.tlb_fillptr)
> > > setup_all_pgtables();
> > >
> > > invalidate_dcache_all();
> > > - __asm_invalidate_tlb_all();
> > > set_sctlr(get_sctlr() | CR_C);
> > > }
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] arm: armv8: Flush TLB before enabling MMU
2026-01-10 19:56 [PATCH] arm: armv8: Flush TLB before enabling MMU Mark Kettenis
` (2 preceding siblings ...)
2026-02-23 21:23 ` Mark Kettenis
@ 2026-02-24 20:02 ` Tom Rini
3 siblings, 0 replies; 6+ messages in thread
From: Tom Rini @ 2026-02-24 20:02 UTC (permalink / raw)
To: u-boot, Mark Kettenis; +Cc: ilias.apalodimas, anshuld, d-gole, casey.connolly
On Sat, 10 Jan 2026 20:56:10 +0100, Mark Kettenis wrote:
> Commit 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on
> dcache_enable") broke Apple Silicon machines in certain scenarios.
> If the MMU is currently not enabled we need to flush the TLB
> before we enable it to prevent stale TLB entries from becoming
> active again. So move the __asm_invalidate_tlb_all() back
> immediately before the mmu_setup() call.
>
> [...]
Applied to u-boot/master, thanks!
[1/1] arm: armv8: Flush TLB before enabling MMU
commit: afa8f076db3e4ff322455e4b13b796f39c30eb14
--
Tom
^ permalink raw reply [flat|nested] 6+ messages in thread