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Mon, 12 Jan 2026 07:08:21 -0600 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE207.ent.ti.com (10.64.6.65) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Mon, 12 Jan 2026 07:08:21 -0600 Received: from localhost (ada0543016.dhcp.ti.com [172.24.233.9]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 60CD8KpP531678; Mon, 12 Jan 2026 07:08:20 -0600 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Date: Mon, 12 Jan 2026 18:38:19 +0530 Message-ID: CC: , , , , , , , , , , , , Subject: Re: [PATCH v2 2/2] ARM: OMAP2+: Pad SPL binary to 8-byte alignment before DTB From: Anshul Dalal To: Beleswar Padhi , X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260112101102.1417970-1-b-padhi@ti.com> <20260112101102.1417970-3-b-padhi@ti.com> In-Reply-To: <20260112101102.1417970-3-b-padhi@ti.com> X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004687:EE_|IA1PR10MB8209:EE_ X-MS-Office365-Filtering-Correlation-Id: bf65bc24-7252-47ce-d825-08de51dbba85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:flwvzet201.ext.ti.com; PTR:ErrorRetry; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(34020700016)(1800799024)(12100799066); DIR:OUT; SFP:1501; X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2026 13:08:50.0946 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf65bc24-7252-47ce-d825-08de51dbba85 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7; Ip=[198.47.21.195]; Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004687.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR10MB8209 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Mon Jan 12, 2026 at 3:41 PM IST, Beleswar Padhi wrote: > The OMAP2 SPL linker script (also used for K3 platforms) currently uses > a 4-byte alignment directive after the __u_boot_list section. This > alignment directive only advances the location counter without padding > the actual binary output. > > When objcopy extracts u-boot-spl-nodtb.bin, it includes only actual > data, stopping at the last byte of __u_boot_list (e.g., 0x41c359fc), > not an aligned address (e.g., 0x41c35a00). So, when the FIT image > containing device trees is concatenated to the SPL binary, it gets > appended at this unaligned file size, causing libfdt validation failure. > > To fix this, move the alignment directive into the __u_boot_list section > itself and make it 8-byte aligned as per DT spec. This forces the linker > to include padding as part of the section data, ensuring objcopy > includes the padding bytes in the binary and the appended FIT image > starts at an 8-byte aligned boundary. > > Reported-by: Anshul Dalal > Closes: https://lore.kernel.org/u-boot/DFJ950O0QM0D.380U0N16ZO19E@ti.com > Fixes: 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g= 52f07dcca47c") > Signed-off-by: Beleswar Padhi > --- > v2: Changelog: > 1. Get rid of extra ALIGN() directive, replace it with a comment > 2. Carry Reported-by, Closes and Fixes tag. > > Link to v1: > https://lore.kernel.org/all/20260109190026.58464-3-b-padhi@ti.com/ > > arch/arm/mach-omap2/u-boot-spl.lds | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-omap2/u-boot-spl.lds b/arch/arm/mach-omap2/u-b= oot-spl.lds > index 3bb759d8a1c..5ad169a37b7 100644 > --- a/arch/arm/mach-omap2/u-boot-spl.lds > +++ b/arch/arm/mach-omap2/u-boot-spl.lds > @@ -35,9 +35,13 @@ SECTIONS > . =3D ALIGN(4); > __u_boot_list : { > KEEP(*(SORT(__u_boot_list*))); > + /* > + * Ensure 8-byte alignment at the end of the last section before > + * DTB is appended, to satisfy DT spec alignment requirements > + */ > + . =3D ALIGN(8); I wonder if there could be a better way to handle this constraint, currently we have two major problems with this approach: 1. All platforms facing similar alignment issues would have to modify their linker scripts. 2. The FDT only gets appended directly to SPL binary in cases of CONFIG_SPL_SEPARATE_BSS. Otherwise we do (SPL binary + BSS + FDT) as per the $(obj)/$(SPL_BIN)-dtb.bin make target. Which means BSS would have to be 8-byte aligned as well as the SPL binary. I wonder if we could have a new make target for say u-boot-spl-nodtb-aligned.bin which is just (SPL binary + optionally BSS + padding for alignment) and at runtime we modify the fdt addr in gd to point to the correctly aligned address? > } >.sram > =20 > - . =3D ALIGN(4); > __image_copy_end =3D .; > _end =3D .; > _image_binary_end =3D .;