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Thu, 15 Jan 2026 22:52:34 -0600 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE206.ent.ti.com (10.64.6.64) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Thu, 15 Jan 2026 22:52:34 -0600 Received: from localhost (ada0543016.dhcp.ti.com [172.24.233.9]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 60G4qW6m2575031; Thu, 15 Jan 2026 22:52:33 -0600 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Date: Fri, 16 Jan 2026 10:22:32 +0530 Message-ID: CC: Tom Rini , Anshul Dalal , "Beleswar Padhi" , , , , , , , , , , , Subject: Re: [PATCH v2 2/2] ARM: OMAP2+: Pad SPL binary to 8-byte alignment before DTB From: Anshul Dalal To: Ilias Apalodimas , Marek Vasut X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260112101102.1417970-1-b-padhi@ti.com> <20260112101102.1417970-3-b-padhi@ti.com> <20260112164854.GQ3416603@bill-the-cat> <8eb4eeea-a755-4032-ab95-2b293f2d2289@mailbox.org> <20260112220536.GU3416603@bill-the-cat> <66ec9e5b-1488-4e35-9a56-91d4b70ff0fa@mailbox.org> <20260113150024.GX3416603@bill-the-cat> <20260114141735.GA3416603@bill-the-cat> <7f1f7601-23ec-4a36-8e2b-3b4b679da6aa@mailbox.org> In-Reply-To: X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A345:EE_|PH0PR10MB4584:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ff94366-315c-42be-532a-08de54bb10b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:flwvzet200.ext.ti.com; PTR:ErrorRetry; CAT:NONE; SFS:(13230040)(376014)(1800799024)(34020700016)(36860700013)(82310400026)(12100799066); DIR:OUT; SFP:1501; X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2026 04:52:34.8159 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ff94366-315c-42be-532a-08de54bb10b6 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7; Ip=[198.47.21.194]; Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A345.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB4584 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Thu Jan 15, 2026 at 1:30 PM IST, Ilias Apalodimas wrote: > Hi Marek, > > > On Thu, 15 Jan 2026 at 02:02, Marek Vasut wrote= : >> >> On 1/14/26 3:17 PM, Tom Rini wrote: >> >> Hello Tom, >> >> >>> OK. And why can't we make that check at $sym rounded up, and ensure = our >> >>> build targets pad? Going back to the commit message here, it's easy = to >> >>> tell the linker to place $sym at the right spot, but it's hard to ma= ke >> >>> sure the output is padded. So having typed all that, maybe we need t= o >> >>> do: >> >>> d) Update linker scripts to ALIGN(8) the above symbols and have the = make >> >>> targets use dd to ensure padding prior to concatenation >> >>> ? >> >> d) looks like what we should do, yes >> > >> > Poking at this harder, I'm not actually sure we need to use dd at all, >> > but we do need to fix our linker scripts, and then going back to when >> > Ilias reworked and cleaned up a bunch of them, get the changes reviewe= d >> > by the toolchain experts he got ahold of :) >> >> I wonder if LD can always guarantee trailing alignment of the binary. If >> it can, then yes, dd would only be obscuring alignment problems and >> trailing DT look up failures which are hard to debug. It would be nice >> to drop the dd part, but I am not sure if we are able to do it reliably. > > LD won't pad align anything that doesn't have code afterwards. IOW > inserting an . =3D ALIGN(8); just before the .end symbol won't guarantee > alignement unless there's a section/code following. > What you can do is add an ALIGN(8) inside the last section. That will > guarantee that the last symbol is aligned. There's also the SUBALIGN > command which messes around with the input section alignment -- that > normally is automatically calculated, but Tom tested it yesterday > without success. > > I'll have a closer look to the linker script in case I can come up > with something more elegant. Which defconfig should I use to reproduce > the issue? We have reproduced the issue on multiple K3 SoCs, to start with you can make use of the am62px_evm_r5_defconfig with arm-none-eabi toolchain from ARM[1] with version 13.3.rel1. [1]: https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads > > Cheers > /Ilias