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charset=UTF-8 Date: Fri, 24 Jul 2026 00:50:31 +0800 Message-Id: From: "Junhui Liu" To: "Eric Chung" , , , Cc: "Tom Rini" , "Peng Fan" , "Huan Zhou" , "Raymond Mao" , "Jaehoon Chung" , "Bhimeswararao Matsa" , "Tanmay Kathpalia" , "Kaustabh Chakraborty" , "Han Xu" , "Yanir Levin" , "Christoph Stoidner" , "Balsundar Ponnusamy" , "Daniel Palmer" , "Anshul Dalal" , "Bastien Curutchet" , "Angelo Dureghello" , "Johan Jonker" , "Rick Chen" , "Leo" , "Sam Protsenko" , "Guodong Xu" , "Tim Ouyang" , "Leo Liang" , "U-Boot" , "Yixun Lan" , "Yao Zi" Subject: Re: [PATCH v4 02/10] pinctrl: k1: add IO power domain configuration support X-Mailer: aerc 0.21.0 References: <20260707-m4-v4-0-dbd01185f911@riscstar.com> <20260707-m4-v4-2-dbd01185f911@riscstar.com> In-Reply-To: <20260707-m4-v4-2-dbd01185f911@riscstar.com> X-ZohoMailClient: External X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1784825448; 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dkim=pass (1024-bit key; unprotected) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="FhhoL6VR"; dkim-atps=neutral X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.u-boot-project.org Sender: "U-Boot" Hi Eric, Thanks for your patch. However, I found a couple of issues while testing. On Tue Jul 7, 2026 at 11:21 PM CST, Eric Chung wrote: > Dual-voltage GPIO banks default to 3.3V, but when externally supplied > with 1.8V the internal logic must be explicitly reconfigured to match. > > Add the ability to program IO power domain control registers through the > APBC block. These registers require unlocking the AIB Secure Access > Register (ASAR) before every read/write, since configuring a 1.8V domain > while 3.3V is externally supplied can cause back-powering and pin damage. > > Signed-off-by: Eric Chung > > --- > v3: > - Add SYSCON dependency in Kconfig. > - Fix not sorted issue in the driver. > --- > drivers/pinctrl/spacemit/Kconfig | 2 +- > drivers/pinctrl/spacemit/pinctrl-k1.c | 83 +++++++++++++++++++++++++++++= +++++- > 2 files changed, 82 insertions(+), 3 deletions(-) > > diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/= Kconfig > index 6aab89e160c..ff754f5839c 100644 > --- a/drivers/pinctrl/spacemit/Kconfig > +++ b/drivers/pinctrl/spacemit/Kconfig > @@ -1,6 +1,6 @@ > config PINCTRL_SPACEMIT_K1 > bool "Spacemit K1 SoC pinctrl driver" > - depends on PINCTRL_GENERIC && DM > + depends on PINCTRL_GENERIC && DM && SYSCON > help > Supports pin multiplexing control on Spacemit K1 SoCs. > =20 > diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spac= emit/pinctrl-k1.c > index 3ebc397213b..95344f4ec72 100644 > --- a/drivers/pinctrl/spacemit/pinctrl-k1.c > +++ b/drivers/pinctrl/spacemit/pinctrl-k1.c [...] > + > static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_se= lector, > unsigned int param, unsigned int argument) > { > @@ -456,6 +526,9 @@ static int spacemit_pinconf_set(struct udevice *dev, = unsigned int pin_selector, > dev_err(dev, "Invalid power source (%d)\n", argument); > return -EINVAL; > } > + if (found) > + spacemit_set_io_power_domain(dev, pin_selector, CONFIG_PINCONF is not enabled in spacemit_k1_defconfig. Therefore, with the default configuration, the generic pinctrl code skips pin configuration properties and spacemit_pinconf_set() is never called. Consequently, the IO power domain configuration added here is not exercised when building with spacemit_k1_defconfig. > + priv->io_pins[i].io_type); > break; > default: > return -EOPNOTSUPP; > @@ -485,6 +558,11 @@ static int spacemit_pinctrl_probe(struct udevice *de= v) > dev_err(dev, "Fail to allocate memory\n"); > return -ENOMEM; > } > + priv->regmap =3D syscon_regmap_lookup_by_phandle(dev, "spacemit,apbc"); > + if (IS_ERR(priv->regmap)) { > + dev_warn(dev, "no syscon found, disable IO power domain switching\n"); > + priv->regmap =3D NULL; > + } The APBC node with compatible "spacemit,k1-syscon-apbc" is bound by drivers/clk/spacemit/clk-k1.c as a UCLASS_CLK device. It is not registered as a UCLASS_SYSCON device, and the node does not have the "syscon" compatible required by the fallback path in syscon_regmap_lookup_by_phandle(). Therefore, this lookup fails and priv->regmap is set to NULL. I added a direct MMIO write to the UART registers here to confirm the failure path. The original dev_warn() is not visible because this probe happens before the normal console is initialized. To fix this, I suggest either making the clock driver register or expose the APBC regmap through the syscon infrastructure, or avoiding syscon here and obtaining the regmap directly using dev_read_phandle_with_args() followed by regmap_init_mem(). > =20 > ret =3D clk_get_bulk(dev, &clks); > if (ret) { > @@ -512,6 +590,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_= data =3D { > .get_pins =3D k1_get_pins, > .get_functions =3D k1_get_functions, > .get_io_type =3D k1_get_io_type, > + .pin_to_io_pd_offset =3D spacemit_k1_pin_to_io_pd_offset, > }; > =20 > static const struct udevice_id spacemit_pinctrl_ids[] =3D { --=20 Best regards, Junhui Liu