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Sat, 7 Nov 2026 01:11:14 -0800 (PST) X-Archived-By: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Sat, 07 Nov 2026 17:11:09 +0800 Message-Id: Cc: "Andre Przywara" , "Tim Ouyang" , "Leo Liang" , "Yao Zi" , "Peng Fan" , "Jaehoon Chung" , "Lukasz Majewski" , "Stefan Roese" , "Samuel Holland" , "Tom Rini" Subject: Re: [PATCH 01/10] riscv: cpu: add Allwinner D1/D1s(F133) CPU support From: "Junhui Liu" To: "Indrek Kruusa" , X-Mailer: aerc 0.22.0 References: <20261101210449.1235102-1-indrek.kruusa@gmail.com> <20261101210449.1235102-2-indrek.kruusa@gmail.com> In-Reply-To: <20261101210449.1235102-2-indrek.kruusa@gmail.com> X-ZohoMailClient: External X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Indrek, Thanks for your work. I'm very happy to finally see someone proposing this work. But for most of the T-Head/XuanTie CPU support, I think it is better to make it common code instead of keeping it private to sun20i. On Mon Nov 2, 2026 at 5:04 AM CST, Indrek Kruusa wrote: > Add the C906 support for the D1/D1s(F133) SoCs: > > - T-Head cache operations from the custom cache instructions > - harts_early_init() programming MXSTATUS, MHCR and MHINT > - cleanup_before_linux() disabling interrupts and flushing the caches > - dram_init() from the device tree memory nodes > - the T-Head CSR, CCU clock and memory map headers > - SUN20I Kconfig (cache line size, T-Head CMO support) > > Signed-off-by: Indrek Kruusa > --- > arch/riscv/Kconfig | 1 + > arch/riscv/cpu/sun20i/Kconfig | 6 ++ > arch/riscv/cpu/sun20i/Makefile | 5 ++ > arch/riscv/cpu/sun20i/cache.c | 88 +++++++++++++++++++ > arch/riscv/cpu/sun20i/cpu.c | 44 ++++++++++ > arch/riscv/cpu/sun20i/dram.c | 21 +++++ > arch/riscv/include/asm/arch-sun20i/clock.h | 71 +++++++++++++++ > arch/riscv/include/asm/arch-sun20i/cpu.h | 18 ++++ > .../riscv/include/asm/arch-sun20i/thead_csr.h | 29 ++++++ > 9 files changed, 283 insertions(+) > create mode 100644 arch/riscv/cpu/sun20i/Kconfig > create mode 100644 arch/riscv/cpu/sun20i/Makefile > create mode 100644 arch/riscv/cpu/sun20i/cache.c > create mode 100644 arch/riscv/cpu/sun20i/cpu.c > create mode 100644 arch/riscv/cpu/sun20i/dram.c > create mode 100644 arch/riscv/include/asm/arch-sun20i/clock.h > create mode 100644 arch/riscv/include/asm/arch-sun20i/cpu.h > create mode 100644 arch/riscv/include/asm/arch-sun20i/thead_csr.h > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 386241efd4a..14c8ca817fb 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -144,6 +144,7 @@ source "arch/riscv/cpu/jh7110/Kconfig" > source "arch/riscv/cpu/k1/Kconfig" > source "arch/riscv/cpu/k3/Kconfig" > source "arch/riscv/cpu/k230/Kconfig" > +source "arch/riscv/cpu/sun20i/Kconfig" > source "arch/riscv/cpu/th1520/Kconfig" > =20 > # architecture-specific options below > diff --git a/arch/riscv/cpu/sun20i/Kconfig b/arch/riscv/cpu/sun20i/Kconfi= g > new file mode 100644 > index 00000000000..7f459518cfe > --- /dev/null > +++ b/arch/riscv/cpu/sun20i/Kconfig > @@ -0,0 +1,6 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +config SUN20I > + bool > + select SYS_CACHE_SHIFT_6 > + select SYS_CACHE_THEAD_CMO if !SYS_DCACHE_OFF > diff --git a/arch/riscv/cpu/sun20i/Makefile b/arch/riscv/cpu/sun20i/Makef= ile > new file mode 100644 > index 00000000000..556aa842ec1 > --- /dev/null > +++ b/arch/riscv/cpu/sun20i/Makefile > @@ -0,0 +1,5 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +obj-y +=3D cache.o > +obj-y +=3D cpu.o > +obj-y +=3D dram.o > diff --git a/arch/riscv/cpu/sun20i/cache.c b/arch/riscv/cpu/sun20i/cache.= c > new file mode 100644 > index 00000000000..c961eded109 > --- /dev/null > +++ b/arch/riscv/cpu/sun20i/cache.c > @@ -0,0 +1,88 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2026, Indrek Kruusa > + * > + * T-Head C906 cache operations for the Allwinner D1 (sun20i). > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +/* > + * T-Head cache maintenance instructions, emitted as raw encodings becau= se the > + * assembler does not know them: dcache.ciall (write back and invalidate= all), > + * dcache.iall (invalidate all), icache.ipa (invalidate the line holding= the > + * physical address in a0) and sync.i (wait for the operation to complet= e). > + * They only decode while MXSTATUS.THEADISAEE is set, which harts_early_= init() > + * does before any of them is used. > + */ > +#define THEAD_SYNC_I ".long 0x01a0000b" > +#define THEAD_DCACHE_CIALL ".long 0x0030000b" > +#define THEAD_DCACHE_IALL ".long 0x0020000b" > +#define THEAD_ICACHE_IPA_A0 ".long 0x0385000b" > + > +static inline void sync_i(void) > +{ > + asm volatile (THEAD_SYNC_I ::: "memory"); > +} > + > +void flush_dcache_all(void) > +{ > + asm volatile (THEAD_DCACHE_CIALL ::: "memory"); > + sync_i(); > +} > + > +void invalidate_dcache_all(void) > +{ > + asm volatile (THEAD_DCACHE_IALL ::: "memory"); > + sync_i(); > +} > + > +void invalidate_icache_range(unsigned long start, unsigned long end) > +{ > + register ulong addr asm ("a0") =3D start & -CONFIG_SYS_CACHELINE_SIZE; > + > + for (; addr < end; addr +=3D CONFIG_SYS_CACHELINE_SIZE) > + asm volatile (THEAD_ICACHE_IPA_A0 :: "r" (addr) : "memory"); > + sync_i(); > +} For these cache operations, arch/riscv/lib/thead_cmo.c already contains the D-cache range operations. The D-cache all operations and I-cache operations added here are common T-Head/XuanTie CMO operations, so I think it's better to add them to that common file instead of being implemented under sun20i. > + > +#if CONFIG_IS_ENABLED(RISCV_MMODE) > + > +void icache_enable(void) > +{ > + invalidate_icache_all(); > + csr_set(CSR_MHCR, MHCR_IE); > +} > + > +void icache_disable(void) > +{ > + csr_clear(CSR_MHCR, MHCR_IE); > +} > + > +int icache_status(void) > +{ > + return csr_read(CSR_MHCR) & MHCR_IE; > +} > + > +void dcache_enable(void) > +{ > + invalidate_dcache_all(); > + csr_set(CSR_MHCR, MHCR_DE); > +} > + > +void dcache_disable(void) > +{ > + flush_dcache_all(); > + csr_clear(CSR_MHCR, MHCR_DE); > +} > + > +int dcache_status(void) > +{ > + return csr_read(CSR_MHCR) & MHCR_DE; > +} > + > +#endif For this part, arch/riscv/cpu/th1520/cache.c already has related functions. Can we extract them into a common file, for example arch/riscv/lib/thead_cache.c, and provide a THEAD_CACHE config for the platforms that need it to select? [...] > diff --git a/arch/riscv/include/asm/arch-sun20i/thead_csr.h b/arch/riscv/= include/asm/arch-sun20i/thead_csr.h > new file mode 100644 > index 00000000000..4d6e15aab1c > --- /dev/null > +++ b/arch/riscv/include/asm/arch-sun20i/thead_csr.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2026, Indrek Kruusa > + * > + * T-Head C906 CSR definitions for the Allwinner D1 (sun20i). > + */ > + > +#ifndef _ASM_RISCV_ARCH_THEAD_CSR_H > +#define _ASM_RISCV_ARCH_THEAD_CSR_H > + > +#define CSR_MXSTATUS 0x7c0 > +#define CSR_MHCR 0x7c1 > +#define CSR_MHINT 0x7c5 > + > +#define MXSTATUS_THEADISAEE BIT(22) /* T-HEAD ISA extensions enable = */ > +#define MXSTATUS_MAEE BIT(21) /* MMU honours the PTE memory ty= pe */ > +#define MXSTATUS_MM BIT(15) /* misaligned access enable */ > + > +#define MHCR_IE BIT(0) /* icache enable */ > +#define MHCR_DE BIT(1) /* dcache enable */ > +#define MHCR_WA BIT(2) /* dcache write allocate */ > +#define MHCR_RS BIT(4) /* return stack enable */ > +#define MHCR_BPE BIT(5) /* branch prediction enable */ > +#define MHCR_BTB_C906 BIT(6) /* branch target prediction enab= le */ > + > +#define MHINT_IPLD BIT(8) /* icache prefetch enable */ > +#define MHINT_IWPE BIT(9) /* icache way prediction enable = */ > + > +#endif /* _ASM_RISCV_ARCH_THEAD_CSR_H */ A number of these CSR definitions already exist in arch/riscv/cpu/th1520/spl.c and arch/riscv/cpu/th1520/cache.c. Can the common register numbers and bitfields be moved into a common header, such as arch/riscv/include/asm/thead_csr.h, instead of placing them under arch-sun20i? --=20 Best regards, Junhui Liu