* [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup
@ 2008-10-23 6:26 Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 01/10] pci: Allow for PCI addresses to be 64-bit Kumar Gala
2008-10-23 8:35 ` [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup Wolfgang Denk
0 siblings, 2 replies; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
This patch series adds the ability to support 64-bit PCI addresses as well
as refactors the fsl_pci_init code and cleans up its users.
Finally it adds some help functions that the board code calls to set
dma-ranges in device trees.
If the particular maintainers could ack the patches that would be great
(Andy, Jon, Jerry).
- k
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 01/10] pci: Allow for PCI addresses to be 64-bit
2008-10-23 6:26 [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup Kumar Gala
@ 2008-10-23 6:26 ` Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 02/10] 85xx: Enable 64-bit PCI resources on all Freescale boards Kumar Gala
2008-10-24 13:12 ` [U-Boot] [PATCH 01/10] pci: Allow for PCI addresses to be 64-bit Wolfgang Denk
2008-10-23 8:35 ` [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup Wolfgang Denk
1 sibling, 2 replies; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
PCI bus is inherently 64-bit. While not all system require access to
the full 64-bit PCI address range some do. This allows those systems
to enable the full PCI address width via CONFIG_SYS_PCI_64BIT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
drivers/pci/pci.c | 37 ++++++++++++++------
drivers/pci/pci_auto.c | 88 ++++++++++++++++++++++++++++-------------------
include/pci.h | 40 +++++++++++++---------
3 files changed, 102 insertions(+), 63 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 41780db..e2b05d8 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -218,12 +218,12 @@ pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
*
*/
-unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
+pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
phys_addr_t phys_addr,
unsigned long flags)
{
struct pci_region *res;
- unsigned long bus_addr;
+ pci_addr_t bus_addr;
int i;
if (!hose) {
@@ -252,7 +252,7 @@ Done:
}
phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
- unsigned long bus_addr,
+ pci_addr_t bus_addr,
unsigned long flags)
{
struct pci_region *res;
@@ -288,15 +288,17 @@ Done:
int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
unsigned long io,
- unsigned long mem,
+ pci_addr_t mem,
unsigned long command)
{
- unsigned int bar_response, bar_size, bar_value, old_command;
+ unsigned int bar_response, old_command;
+ pci_addr_t bar_value;
+ pci_size_t bar_size;
unsigned char pin;
int bar, found_mem64;
- debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
- io, mem, command);
+ debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
+ io, (u64)mem, command);
pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
@@ -319,10 +321,19 @@ int pci_hose_config_device(struct pci_controller *hose,
io = io + bar_size;
} else {
if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64)
- found_mem64 = 1;
+ PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ u32 bar_response_upper;
+ u64 bar64;
+ pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
+ pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
- bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+ bar64 = ((u64)bar_response_upper << 32) | bar_response;
+
+ bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+ found_mem64 = 1;
+ } else {
+ bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
+ }
/* round up region base address to multiple of size */
mem = ((mem - 1) | (bar_size - 1)) + 1;
@@ -332,11 +343,15 @@ int pci_hose_config_device(struct pci_controller *hose,
}
/* Write it out and update our limit */
- pci_hose_write_config_dword (hose, dev, bar, bar_value);
+ pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
if (found_mem64) {
bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
+#else
pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
+#endif
}
}
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 3844359..c20b981 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -45,14 +45,14 @@ void pciauto_region_init(struct pci_region* res)
res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
}
-void pciauto_region_align(struct pci_region *res, unsigned long size)
+void pciauto_region_align(struct pci_region *res, pci_size_t size)
{
res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
}
-int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
+int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar)
{
- unsigned long addr;
+ pci_addr_t addr;
if (!res) {
DEBUGF("No resource");
@@ -68,13 +68,13 @@ int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned
res->bus_lower = addr + size;
- DEBUGF("address=0x%lx bus_lower=%x", addr, res->bus_lower);
+ DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
*bar = addr;
return 0;
error:
- *bar = 0xffffffff;
+ *bar = (pci_addr_t)-1;
return -1;
}
@@ -88,7 +88,9 @@ void pciauto_setup_device(struct pci_controller *hose,
struct pci_region *prefetch,
struct pci_region *io)
{
- unsigned int bar_value, bar_response, bar_size;
+ unsigned int bar_response;
+ pci_addr_t bar_value;
+ pci_size_t bar_size;
unsigned int cmdstat = 0;
struct pci_region *bar_res;
int bar, bar_nr = 0;
@@ -114,33 +116,46 @@ void pciauto_setup_device(struct pci_controller *hose,
& 0xffff) + 1;
bar_res = io;
- DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
+ DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
} else {
if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64)
- found_mem64 = 1;
+ PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ u32 bar_response_upper;
+ u64 bar64;
+ pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
+ pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
+
+ bar64 = ((u64)bar_response_upper << 32) | bar_response;
- bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+ bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+ found_mem64 = 1;
+ } else {
+ bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
+ }
if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
bar_res = prefetch;
else
bar_res = mem;
- DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
+ DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
}
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
/* Write it out and update our limit */
- pci_hose_write_config_dword(hose, dev, bar, bar_value);
+ pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
- /*
- * If we are a 64-bit decoder then increment to the
- * upper 32 bits of the bar and force it to locate
- * in the lower 4GB of memory.
- */
if (found_mem64) {
bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
+#else
+ /*
+ * If we are a 64-bit decoder then increment to the
+ * upper 32 bits of the bar and force it to locate
+ * in the lower 4GB of memory.
+ */
pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
+#endif
}
cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
@@ -289,35 +304,36 @@ void pciauto_config_init(struct pci_controller *hose)
if (hose->pci_mem) {
pciauto_region_init(hose->pci_mem);
- DEBUGF("PCI Autoconfig: Bus Memory region: [%lx-%lx],\n"
- "\t\tPhysical Memory [%x-%x]\n",
- hose->pci_mem->bus_start,
- hose->pci_mem->bus_start + hose->pci_mem->size - 1,
- hose->pci_mem->phys_start,
- hose->pci_mem->phys_start + hose->pci_mem->size - 1);
+ DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
+ "\t\tPhysical Memory [%llx-%llxx]\n",
+ (u64)hose->pci_mem->bus_start,
+ (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
+ (u64)hose->pci_mem->phys_start,
+ (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
}
if (hose->pci_prefetch) {
pciauto_region_init(hose->pci_prefetch);
- DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [%lx-%lx],\n"
- "\t\tPhysical Memory [%x-%x]\n",
- hose->pci_prefetch->bus_start,
- hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1,
- hose->pci_prefetch->phys_start,
- hose->pci_prefetch->phys_start +
- hose->pci_prefetch->size - 1);
+ DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
+ "\t\tPhysical Memory [%llx-%llx]\n",
+ (u64)hose->pci_prefetch->bus_start,
+ (u64)(hose->pci_prefetch->bus_start +
+ hose->pci_prefetch->size - 1),
+ (u64)hose->pci_prefetch->phys_start,
+ (u64)(hose->pci_prefetch->phys_start +
+ hose->pci_prefetch->size - 1));
}
if (hose->pci_io) {
pciauto_region_init(hose->pci_io);
- DEBUGF("PCI Autoconfig: Bus I/O region: [%lx-%lx],\n"
- "\t\tPhysical Memory: [%x-%x]\n",
- hose->pci_io->bus_start,
- hose->pci_io->bus_start + hose->pci_io->size - 1,
- hose->pci_io->phys_start,
- hose->pci_io->phys_start + hose->pci_io->size - 1);
+ DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
+ "\t\tPhysical Memory: [%llx-%llx]\n",
+ (u64)hose->pci_io->bus_start,
+ (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
+ (u64)hose->pci_io->phys_start,
+ (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
}
}
diff --git a/include/pci.h b/include/pci.h
index 1c8e216..eebe8a8 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -101,8 +101,8 @@
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
-#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
-#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
+#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
+#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
@@ -111,7 +111,7 @@
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE 0x01
-#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
+#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
@@ -312,13 +312,21 @@
#include <pci_ids.h>
+#ifdef CONFIG_SYS_PCI_64BIT
+typedef u64 pci_addr_t;
+typedef u64 pci_size_t;
+#else
+typedef u32 pci_addr_t;
+typedef u32 pci_size_t;
+#endif
+
struct pci_region {
- unsigned long bus_start; /* Start on the bus */
- phys_addr_t phys_start; /* Start in physical address space */
- unsigned long size; /* Size */
- unsigned long flags; /* Resource flags */
+ pci_addr_t bus_start; /* Start on the bus */
+ phys_addr_t phys_start; /* Start in physical address space */
+ pci_size_t size; /* Size */
+ unsigned long flags; /* Resource flags */
- unsigned long bus_lower;
+ pci_addr_t bus_lower;
};
#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
@@ -330,9 +338,9 @@ struct pci_region {
#define PCI_REGION_RO 0x00000200 /* Read-only memory */
extern __inline__ void pci_set_region(struct pci_region *reg,
- unsigned long bus_start,
+ pci_addr_t bus_start,
phys_addr_t phys_start,
- unsigned long size,
+ pci_size_t size,
unsigned long flags) {
reg->bus_start = bus_start;
reg->phys_start = phys_start;
@@ -433,9 +441,9 @@ extern __inline__ void pci_set_ops(struct pci_controller *hose,
extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
- unsigned long addr, unsigned long flags);
-extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
- phys_addr_t addr, unsigned long flags);
+ pci_addr_t addr, unsigned long flags);
+extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
+ phys_addr_t addr, unsigned long flags);
#define pci_phys_to_bus(dev, addr, flags) \
pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
@@ -483,8 +491,8 @@ extern int pci_hose_scan(struct pci_controller *hose);
extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
extern void pciauto_region_init(struct pci_region* res);
-extern void pciauto_region_align(struct pci_region *res, unsigned long size);
-extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
+extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
+extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
extern void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
@@ -500,7 +508,7 @@ extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
extern int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
unsigned long io,
- unsigned long mem,
+ pci_addr_t mem,
unsigned long command);
#ifdef CONFIG_MPC824X
--
1.5.5.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 02/10] 85xx: Enable 64-bit PCI resources on all Freescale boards
2008-10-23 6:26 ` [U-Boot] [PATCH 01/10] pci: Allow for PCI addresses to be 64-bit Kumar Gala
@ 2008-10-23 6:26 ` Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 03/10] 86xx: " Kumar Gala
2008-10-24 13:12 ` [U-Boot] [PATCH 01/10] pci: Allow for PCI addresses to be 64-bit Wolfgang Denk
1 sibling, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
include/configs/MPC8536DS.h | 1 +
include/configs/MPC8540ADS.h | 1 +
include/configs/MPC8541CDS.h | 1 +
include/configs/MPC8544DS.h | 1 +
include/configs/MPC8548CDS.h | 1 +
include/configs/MPC8555CDS.h | 1 +
include/configs/MPC8560ADS.h | 1 +
include/configs/MPC8568MDS.h | 1 +
include/configs/MPC8572DS.h | 1 +
9 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 38be10d..d990f11 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -41,6 +41,7 @@
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5a14969..79a52d9 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -46,6 +46,7 @@
#endif
#define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index eede26a..7ada8a2 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -38,6 +38,7 @@
#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
#define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 0987448..c47374a 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -41,6 +41,7 @@
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 892c52e..b67de56 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -43,6 +43,7 @@
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 41870f1..f9419cc 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -38,6 +38,7 @@
#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
#define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 0d3a500..f67d489 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -43,6 +43,7 @@
#define CONFIG_MPC8560 1
#define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index ba2f152..c4d4374 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -38,6 +38,7 @@
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 5688589..06696f0 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -42,6 +42,7 @@
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 03/10] 86xx: Enable 64-bit PCI resources on all Freescale boards
2008-10-23 6:26 ` [U-Boot] [PATCH 02/10] 85xx: Enable 64-bit PCI resources on all Freescale boards Kumar Gala
@ 2008-10-23 6:26 ` Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers Kumar Gala
0 siblings, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
include/configs/MPC8610HPCD.h | 1 +
include/configs/MPC8641HPCN.h | 1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 678e1e1..0492274 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -41,6 +41,7 @@
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index e5710c0..ceb2c69 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -49,6 +49,7 @@
#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers
2008-10-23 6:26 ` [U-Boot] [PATCH 03/10] 86xx: " Kumar Gala
@ 2008-10-23 6:26 ` Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 05/10] fdt: Added helper to set PCI dma-ranges property Kumar Gala
2008-10-23 11:55 ` [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers Jerry Van Baren
0 siblings, 2 replies; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
Add helper functions to return top level #size-cell and #address-cell info
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
include/fdt_support.h | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/include/fdt_support.h b/include/fdt_support.h
index ceaadc2..aa9d86b 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -28,6 +28,24 @@
#include <fdt.h>
+static inline int fdt_addrcell(void *blob) {
+ const u32 *addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
+
+ if (addrcell)
+ return *addrcell;
+ else
+ return 1;
+}
+
+static inline int fdt_sizecell(void *blob) {
+ const u32 *sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
+
+ if (sizecell)
+ return *sizecell;
+ else
+ return 1;
+}
+
int fdt_chosen(void *fdt, int force);
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
void do_fixup_by_path(void *fdt, const char *path, const char *prop,
--
1.5.5.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 05/10] fdt: Added helper to set PCI dma-ranges property
2008-10-23 6:26 ` [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers Kumar Gala
@ 2008-10-23 6:26 ` Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 06/10] pci/fsl_pci_init: Enable larger address and setting inbound windows properly Kumar Gala
2008-10-23 11:55 ` [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers Jerry Van Baren
1 sibling, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
Added fdt_pci_dma_ranges() that parses the pci_region info from the
struct pci_controller and populates the dma-ranges based on it.
The max # of windws/dma-ranges we support is 3 since on embedded
PowerPC based systems this is the max number of windows.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
common/fdt_support.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++
include/fdt_support.h | 5 +++
2 files changed, 74 insertions(+), 0 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 8ceeb0f..9f1cc3d 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -593,3 +593,72 @@ int fdt_resize(void *blob)
return actualsize;
}
+
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_PCI_NR_INBOUND_WIN 3
+
+#define FDT_PCI_PREFETCH (0x40000000)
+#define FDT_PCI_MEM32 (0x02000000)
+#define FDT_PCI_IO (0x01000000)
+#define FDT_PCI_MEM64 (0x03000000)
+
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
+
+ int addrcell, sizecell, len, r;
+ u32 *dma_range;
+ /* sized based on pci addr cells, size-cells, & address-cells */
+ u32 dma_ranges[(3 + 2 + 2) * CONFIG_SYS_PCI_NR_INBOUND_WIN];
+
+ addrcell = fdt_addrcell(blob);
+ sizecell = fdt_sizecell(blob);
+
+ dma_range = &dma_ranges[0];
+ for (r = 0; r < hose->region_count; r++) {
+ u64 bus_start, phys_start, size;
+
+ /* skip if !PCI_REGION_MEMORY */
+ if (!(hose->regions[r].flags & PCI_REGION_MEMORY))
+ continue;
+
+ bus_start = (u64)hose->regions[r].bus_start;
+ phys_start = (u64)hose->regions[r].phys_start;
+ size = (u64)hose->regions[r].size;
+
+ dma_range[0] = 0;
+ if (size > 0x100000000ull)
+ dma_range[0] |= FDT_PCI_MEM64;
+ else
+ dma_range[0] |= FDT_PCI_MEM32;
+ if (hose->regions[r].flags & PCI_REGION_PREFETCH)
+ dma_range[0] |= FDT_PCI_PREFETCH;
+#ifdef CONFIG_SYS_PCI_64BIT
+ dma_range[1] = bus_start >> 32;
+#else
+ dma_range[1] = 0;
+#endif
+ dma_range[2] = bus_start & 0xffffffff;
+
+ if (addrcell == 2) {
+ dma_range[3] = phys_start >> 32;
+ dma_range[4] = phys_start & 0xffffffff;
+ } else {
+ dma_range[3] = phys_start & 0xffffffff;
+ }
+
+ if (sizecell == 2) {
+ dma_range[3 + addrcell + 0] = size >> 32;
+ dma_range[3 + addrcell + 1] = size & 0xffffffff;
+ } else {
+ dma_range[3 + addrcell + 0] = size & 0xffffffff;
+ }
+
+ dma_range += (3 + addrcell + sizecell);
+ }
+
+ len = dma_range - &dma_ranges[0];
+ if (len)
+ fdt_setprop(blob, phb_off, "dma-ranges", &dma_ranges[0], len*4);
+
+ return 0;
+}
+#endif
diff --git a/include/fdt_support.h b/include/fdt_support.h
index aa9d86b..5c932de 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -81,6 +81,11 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev);
static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
#endif
+#ifdef CONFIG_PCI
+#include <pci.h>
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
+#endif
+
#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup(void *blob, bd_t *bd);
void ft_cpu_setup(void *blob, bd_t *bd);
--
1.5.5.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 06/10] pci/fsl_pci_init: Enable larger address and setting inbound windows properly
2008-10-23 6:26 ` [U-Boot] [PATCH 05/10] fdt: Added helper to set PCI dma-ranges property Kumar Gala
@ 2008-10-23 6:26 ` Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 07/10] pci/fsl_pci_init: Add a common PCI inbound setup function Kumar Gala
0 siblings, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
* PCI Inbound window was setup incorrectly. The PCI address and system
address were swapped. The PCI address should be setting piwar/piwbear
and the system address should be setting pitar.
* Removed masking of addresses to allow for system address to support
system address & PCI address >32-bits
* Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses
* Respect the PCI_REGION_PREFETCH for inbound windows
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
drivers/pci/fsl_pci_init.c | 38 ++++++++++++++++++++++++--------------
1 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 38a16e5..f41c8aa 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -39,10 +39,9 @@ void pciauto_prescan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus);
void pciauto_postscan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus);
-
void pciauto_config_init(struct pci_controller *hose);
-void
-fsl_pci_init(struct pci_controller *hose)
+
+void fsl_pci_init(struct pci_controller *hose)
{
u16 temp16;
u32 temp32;
@@ -65,25 +64,36 @@ fsl_pci_init(struct pci_controller *hose)
#endif
for (r=0; r<hose->region_count; r++) {
+ u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
- pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
- pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
+ u32 flag = PIWAR_EN | PIWAR_LOCAL | \
+ PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+ pi->pitar = (hose->regions[r].phys_start >> 12);
+ pi->piwbar = (hose->regions[r].bus_start >> 12);
+#ifdef CONFIG_SYS_PCI_64BIT
+ pi->piwbear = (hose->regions[r].bus_start >> 44);
+#else
pi->piwbear = 0;
- pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP |
- (__ilog2(hose->regions[r].size) - 1);
+#endif
+ if (hose->regions[r].flags & PCI_REGION_PREFETCH)
+ flag |= PIWAR_PF;
+ pi->piwar = flag | sz;
pi++;
inbound = hose->regions[r].size > 0;
} else { /* Outbound */
- po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
- po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
+ po->powbar = (hose->regions[r].phys_start >> 12);
+ po->potar = (hose->regions[r].bus_start >> 12);
+#ifdef CONFIG_SYS_PCI_64BIT
+ po->potear = (hose->regions[r].bus_start >> 44);
+#else
po->potear = 0;
+#endif
if (hose->regions[r].flags & PCI_REGION_IO)
- po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE |
- (__ilog2(hose->regions[r].size) - 1);
+ po->powar = POWAR_EN | sz | \
+ POWAR_IO_READ | POWAR_IO_WRITE;
else
- po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE |
- (__ilog2(hose->regions[r].size) - 1);
+ po->powar = POWAR_EN | sz | \
+ POWAR_MEM_READ | POWAR_MEM_WRITE;
po++;
}
}
--
1.5.5.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 07/10] pci/fsl_pci_init: Add a common PCI inbound setup function
2008-10-23 6:26 ` [U-Boot] [PATCH 06/10] pci/fsl_pci_init: Enable larger address and setting inbound windows properly Kumar Gala
@ 2008-10-23 6:26 ` Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 08/10] pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges Kumar Gala
0 siblings, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
Add a common setup function that determines the pci_region(s) based
on how much memory we have in the system.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
drivers/pci/fsl_pci_init.c | 81 ++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 81 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index f41c8aa..564459c 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -18,6 +18,8 @@
#include <common.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
*
@@ -41,6 +43,85 @@ void pciauto_postscan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus);
void pciauto_config_init(struct pci_controller *hose);
+#ifndef CONFIG_SYS_PCI_MEMORY_BUS
+#define CONFIG_SYS_PCI_MEMORY_BUS 0
+#endif
+
+#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
+#define CONFIG_SYS_PCI_MEMORY_PHYS 0
+#endif
+
+#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
+#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
+#endif
+
+int fsl_pci_setup_inbound_windows(struct pci_region *r)
+{
+ struct pci_region *rgn_base = r;
+ u64 sz = min((u64)gd->ram_size, 1ull << 32);
+
+ phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
+ pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
+ pci_size_t pci_sz = 1ull << __ilog2_u64(sz);
+
+ debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
+ (u64)bus_start, (u64)phys_start, (u64)pci_sz);
+ pci_set_region(r++, bus_start, phys_start, pci_sz,
+ PCI_REGION_MEM | PCI_REGION_MEMORY | \
+ PCI_REGION_PREFETCH);
+
+ sz -= pci_sz;
+ bus_start += pci_sz;
+ phys_start += pci_sz;
+
+ pci_sz = 1ull << __ilog2_u64(sz);
+ if (sz) {
+ debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
+ (u64)bus_start, (u64)phys_start, (u64)pci_sz);
+ pci_set_region(r++, bus_start, phys_start, pci_sz,
+ PCI_REGION_MEM | PCI_REGION_MEMORY | \
+ PCI_REGION_PREFETCH);
+ sz -= pci_sz;
+ bus_start += pci_sz;
+ phys_start += pci_sz;
+ }
+
+#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
+ pci_sz = 1ull << __ilog2_u64(gd->ram_size);
+ /* round up to the next largest power of two */
+ if (gd->ram_size > pci_sz)
+ sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
+ debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
+ (u64)CONFIG_SYS_PCI_MEMORY_BUS,
+ (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
+ (u64)pci_sz);
+ pci_set_region(r++,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ pci_sz,
+ PCI_REGION_MEM | PCI_REGION_MEMORY | \
+ PCI_REGION_PREFETCH);
+#else
+ pci_sz = 1ull << __ilog2_u64(sz);
+ if (sz) {
+ debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
+ (u64)bus_start, (u64)phys_start, (u64)pci_sz);
+ pci_set_region(r++, bus_start, phys_start, pci_sz,
+ PCI_REGION_MEM | PCI_REGION_MEMORY | \
+ PCI_REGION_PREFETCH);
+ sz -= pci_sz;
+ bus_start += pci_sz;
+ phys_start += pci_sz;
+ }
+#endif
+
+ if (sz && (((u64)gd->ram_size) < (1ull << 32)))
+ printf("Was not able to map all of memory via "
+ "inbound windows -- %lld remaining\n", sz);
+
+ return r - rgn_base;
+}
+
void fsl_pci_init(struct pci_controller *hose)
{
u16 temp16;
--
1.5.5.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 08/10] pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges
2008-10-23 6:26 ` [U-Boot] [PATCH 07/10] pci/fsl_pci_init: Add a common PCI inbound setup function Kumar Gala
@ 2008-10-23 6:26 ` Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 09/10] 85xx: Convert all fsl_pci_init users to new APIs Kumar Gala
0 siblings, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
drivers/pci/fsl_pci_init.c | 20 ++++++++++++++++++++
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 564459c..b5d868f 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -299,3 +299,23 @@ void fsl_pci_init(struct pci_controller *hose)
pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
}
}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose)
+{
+ int off = fdt_path_offset(blob, pci_alias);
+
+ if (off >= 0) {
+ u32 bus_range[2];
+
+ bus_range[0] = 0;
+ bus_range[1] = hose->last_busno - hose->first_busno;
+ fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
+ fdt_pci_dma_ranges(blob, off, hose);
+ }
+}
+#endif
--
1.5.5.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 09/10] 85xx: Convert all fsl_pci_init users to new APIs
2008-10-23 6:26 ` [U-Boot] [PATCH 08/10] pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges Kumar Gala
@ 2008-10-23 6:26 ` Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 10/10] 86xx: " Kumar Gala
0 siblings, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().
With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
board/atum8548/atum8548.c | 77 +++++++---------------
board/freescale/mpc8536ds/mpc8536ds.c | 110 ++++++++++--------------------
board/freescale/mpc8544ds/mpc8544ds.c | 109 ++++++++++--------------------
board/freescale/mpc8548cds/mpc8548cds.c | 57 +++++-----------
board/freescale/mpc8568mds/mpc8568mds.c | 56 +++++----------
board/freescale/mpc8572ds/mpc8572ds.c | 72 +++++++-------------
board/sbc8548/sbc8548.c | 66 ++++++-------------
board/tqc/tqm85xx/tqm85xx.c | 58 ++++++-----------
include/configs/ATUM8548.h | 5 --
include/configs/MPC8536DS.h | 5 --
include/configs/MPC8544DS.h | 5 --
include/configs/MPC8548CDS.h | 5 --
include/configs/MPC8568MDS.h | 5 --
include/configs/MPC8572DS.h | 5 --
include/configs/TQM85xx.h | 5 --
include/configs/sbc8548.h | 5 --
16 files changed, 200 insertions(+), 445 deletions(-)
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c
index 2ef19ce..7b7a968 100644
--- a/board/atum8548/atum8548.c
+++ b/board/atum8548/atum8548.c
@@ -182,6 +182,9 @@ static struct pci_controller pcie1_hose;
int first_free_busno=0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
void
pci_init_board(void)
{
@@ -211,10 +214,10 @@ pci_init_board(void)
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
int pcie_configured = io_sel & 6;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE1 connected to slot as %s (base address %x)",
@@ -227,36 +230,31 @@ pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -279,8 +277,8 @@ pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
uint pci_agent = (host_agent == 6);
uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
@@ -300,26 +298,22 @@ pci_init_board(void)
);
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -340,26 +334,23 @@ pci_init_board(void)
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
+ struct pci_region *r = hose->regions;
if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BASE,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -385,39 +376,21 @@ int last_stage_init(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
-void
-ft_board_setup(void *blob, bd_t *bd)
+void ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
- }
}
#endif
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index f357826..2978b7d 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -155,6 +155,9 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno=0;
void
@@ -181,10 +184,10 @@ pci_init_board(void)
#ifdef CONFIG_PCIE3
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 1);
int pcie_configured = (io_sel == 7);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
@@ -197,27 +200,23 @@ pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -239,11 +238,11 @@ pci_init_board(void)
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
int pcie_configured = (io_sel == 2 || io_sel == 3
|| io_sel == 5 || io_sel == 7);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
@@ -256,36 +255,31 @@ pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -308,10 +302,10 @@ pci_init_board(void)
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 3);
int pcie_configured = (io_sel == 5 || io_sel == 7);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
@@ -324,36 +318,31 @@ pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE2,
CONFIG_SYS_PCIE2_MEM_PHYS2,
CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -375,8 +364,8 @@ pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
uint pci_agent = (host_agent == 6);
uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
@@ -397,35 +386,31 @@ pci_init_board(void)
);
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+
#ifdef CONFIG_SYS_PCI1_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE2,
CONFIG_SYS_PCI1_MEM_PHYS2,
CONFIG_SYS_PCI1_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -660,45 +645,24 @@ int board_eth_init(bd_t *bis)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- int node, tmp[2];
- const char *path;
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+void ft_board_setup(void *blob, bd_t *bd)
+{
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
-#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+#ifdef CONFIG_PCIE2
+ ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
-#ifdef CONFIG_PCIE3
- path = fdt_getprop(blob, node, "pci3", NULL);
- if (path) {
- tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+#ifdef CONFIG_PCIE1
+ ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
#endif
- }
}
#endif
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 826180c..600d606 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -103,6 +103,9 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno=0;
void
@@ -126,10 +129,10 @@ pci_init_board(void)
#ifdef CONFIG_PCIE3
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 1);
int pcie_configured = io_sel >= 1;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE3 connected to ULI as %s (base address %x)",
@@ -142,36 +145,31 @@ pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE2,
CONFIG_SYS_PCIE3_MEM_PHYS2,
CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -198,10 +196,10 @@ pci_init_board(void)
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
int pcie_configured = io_sel & 6;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
@@ -214,36 +212,31 @@ pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -266,10 +259,10 @@ pci_init_board(void)
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 3);
int pcie_configured = io_sel & 4;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
@@ -282,36 +275,31 @@ pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE2,
CONFIG_SYS_PCIE2_MEM_PHYS2,
CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -333,8 +321,8 @@ pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
uint pci_agent = (host_agent == 6);
uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
@@ -355,35 +343,31 @@ pci_init_board(void)
);
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+
#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE2,
CONFIG_SYS_PCIE3_MEM_PHYS2,
CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -503,46 +487,25 @@ int board_eth_init(bd_t *bis)
}
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
-void
-ft_board_setup(void *blob, bd_t *bd)
+void ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
+
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE3
- path = fdt_getprop(blob, node, "pci3", NULL);
- if (path) {
- tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
#endif
- }
}
#endif
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 875628d..6eb62ea 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -285,6 +285,9 @@ static struct pci_controller pci2_hose;
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno=0;
void
@@ -298,9 +301,9 @@ pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
struct pci_config_table *table;
+ struct pci_region *r = hose->regions;
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
@@ -322,27 +325,22 @@ pci_init_board(void)
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
/* relocate config table pointers */
hose->config_table = \
@@ -393,9 +391,9 @@ pci_init_board(void)
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+ struct pci_region *r = hose->regions;
int pcie_configured = io_sel >= 1;
@@ -411,27 +409,23 @@ pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -484,29 +478,16 @@ int last_stage_init(void)
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- int node, tmp[2];
- const char *path;
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
+void ft_pci_setup(void *blob, bd_t *bd)
+{
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
- }
}
#endif
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index eab1900..28e3892 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -323,6 +323,9 @@ static struct pci_controller pci1_hose = {
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno = 0;
/*
@@ -380,8 +383,8 @@ pci_init_board(void)
pib_init();
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
uint pci_32 = 1; /* PORDEVSR[15] */
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
@@ -402,27 +405,23 @@ pci_init_board(void)
);
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -441,9 +440,9 @@ pci_init_board(void)
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+ struct pci_region *r = hose->regions;
int pcie_configured = io_sel >= 1;
@@ -459,27 +458,23 @@ pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -500,31 +495,18 @@ pci_init_board(void)
#endif /* CONFIG_PCI */
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- int node, tmp[2];
- const char *path;
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+void ft_board_setup(void *blob, bd_t *bd)
+{
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
- }
}
#endif
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index b2402dc..d1528a7 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -147,6 +147,9 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno=0;
#ifdef CONFIG_PCI
void pci_init_board(void)
@@ -172,11 +175,11 @@ void pci_init_board(void)
#ifdef CONFIG_PCIE3
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
(host_agent == 5) || (host_agent == 6);
int pcie_configured = io_sel >= 1;
+ struct pci_region *r = hose->regions;
u32 temp32;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -190,27 +193,23 @@ void pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -244,11 +243,11 @@ void pci_init_board(void)
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
(host_agent == 6) || (host_agent == 0);
int pcie_configured = io_sel & 4;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
@@ -261,27 +260,23 @@ void pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -301,11 +296,11 @@ void pci_init_board(void)
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
(host_agent == 5);
int pcie_configured = io_sel & 6;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
@@ -318,27 +313,23 @@ void pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -568,10 +559,11 @@ int board_eth_init(bd_t *bis)
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+
void ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
ulong base, size;
ft_cpu_setup(blob, bd);
@@ -581,31 +573,15 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCIE3
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
- }
}
#endif
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 21f82f2..e27c92d 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -364,6 +364,9 @@ static struct pci_controller pcie1_hose;
int first_free_busno=0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
void
pci_init_board(void)
{
@@ -372,9 +375,9 @@ pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
struct pci_config_table *table;
+ struct pci_region *r = hose->regions;
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
@@ -396,27 +399,22 @@ pci_init_board(void)
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
/* relocate config table pointers */
hose->config_table = \
@@ -467,9 +465,9 @@ pci_init_board(void)
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+ struct pci_region *r = hose->regions;
int pcie_configured = io_sel >= 1;
@@ -485,27 +483,27 @@ pci_init_board(void)
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
+ pci_set_region(r++,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -531,41 +529,17 @@ int last_stage_init(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- int node, tmp[2];
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
- const char *path;
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
- const char *path;
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
- }
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
}
#endif
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 1f309bb..97d49ea 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -538,6 +538,9 @@ void local_bus_init (void)
*/
static int first_free_busno;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI || CONFIG_PCI1 */
@@ -552,8 +555,8 @@ static inline void init_pci1(void)
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
/* PORDEVSR[15] */
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
@@ -578,28 +581,23 @@ static inline void init_pci1(void)
/* inbound */
- pci_set_region (hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region (hose->regions + 1,
+ pci_set_region (r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region (hose->regions + 2,
+ pci_set_region (r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect (hose, (int)&pci->cfg_addr,
@@ -641,10 +639,10 @@ static inline void init_pcie1(void)
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) ||
(host_agent == 3);
+ struct pci_region *r = hose->regions;
int pcie_configured = io_sel >= 1;
@@ -660,27 +658,23 @@ static inline void init_pcie1(void)
puts ("\n");
/* inbound */
- pci_set_region (hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region (hose->regions + 1,
+ pci_set_region (r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region (hose->regions + 2,
+ pci_set_region (r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
@@ -707,31 +701,19 @@ void pci_init_board (void)
}
#ifdef CONFIG_OF_BOARD_SETUP
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+
void ft_board_setup (void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup (blob, bd);
- node = fdt_path_offset (blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
- path = fdt_getprop (blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif /* CONFIG_PCI || CONFIG_PCI1 */
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop (blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif /* CONFIG_PCIE1 */
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
+#endif
}
#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 2450adb..1b74526 100644
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -287,11 +287,6 @@
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index d990f11..bdecfa0 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -315,11 +315,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index c47374a..cdbbea6 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -276,11 +276,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
/* controller 2, Slot 1, tgtid 1, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_BASE 0x80000000
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index b67de56..083afba 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -420,11 +420,6 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#endif /* CONFIG_PCI */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index c4d4374..ab3e6d6 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -389,11 +389,6 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#endif /* CONFIG_PCI */
#ifndef CONFIG_NET_MULTI
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 06696f0..fbb8970 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -336,11 +336,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
#define CONFIG_SYS_PCIE3_MEM_BASE 0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index b05f43d..2d4048a 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -403,11 +403,6 @@
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#ifdef CONFIG_PCIE1
/*
* General PCI express
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 54f3e66..aefd30a 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -387,11 +387,6 @@
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#endif /* CONFIG_PCI */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 10/10] 86xx: Convert all fsl_pci_init users to new APIs
2008-10-23 6:26 ` [U-Boot] [PATCH 09/10] 85xx: Convert all fsl_pci_init users to new APIs Kumar Gala
@ 2008-10-23 6:26 ` Kumar Gala
2008-10-24 0:41 ` Jon Loeliger
0 siblings, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 6:26 UTC (permalink / raw)
To: u-boot
Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use
fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup().
With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
board/freescale/mpc8610hpcd/mpc8610hpcd.c | 78 +++++++++--------------------
board/freescale/mpc8641hpcn/mpc8641hpcn.c | 53 ++++++-------------
board/sbc8641d/sbc8641d.c | 55 +++++++--------------
include/configs/MPC8610HPCD.h | 5 --
include/configs/MPC8641HPCN.h | 5 --
include/configs/sbc8641d.h | 5 --
6 files changed, 59 insertions(+), 142 deletions(-)
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 5faeca1..dacd2a9 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -240,6 +240,9 @@ static struct pci_controller pcie2_hose;
int first_free_busno = 0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
@@ -256,11 +259,11 @@ void pci_init_board(void)
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_configured = (io_sel == 1) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
(host_agent == 5);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
@@ -270,27 +273,23 @@ void pci_init_board(void)
pci->pme_msg_det = 0xffffffff;
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
@@ -313,8 +312,8 @@ void pci_init_board(void)
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
+ struct pci_region *r = hose->regions;
int pcie_configured = (io_sel == 0) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
@@ -329,27 +328,23 @@ void pci_init_board(void)
pci->pme_msg_det = 0xffffffff;
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
@@ -371,9 +366,9 @@ void pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
int pci_agent = (host_agent >= 4) && (host_agent <= 6);
+ struct pci_region *r = hose->regions;
if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
printf(" PCI connected to PCI slots as %s" \
@@ -382,27 +377,23 @@ void pci_init_board(void)
(uint)pci);
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr,
@@ -422,12 +413,12 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+
void
ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
@@ -442,36 +433,15 @@ ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
-
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
-
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno
- - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno
- - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
#endif
- }
}
#endif
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index fcaaacb..6b4d6ce 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -161,6 +161,8 @@ static struct pci_controller pci2_hose;
int first_free_busno = 0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
void pci_init_board(void)
{
@@ -173,8 +175,9 @@ void pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
+
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
>> MPC8641_PORBMSR_HA_SHIFT;
@@ -193,27 +196,23 @@ void pci_init_board(void)
debug("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -242,32 +241,27 @@ void pci_init_board(void)
#ifdef CONFIG_PCI2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
-
+ struct pci_region *r = hose->regions;
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BASE,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -286,33 +280,20 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
void
ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
- }
}
#endif
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 06d1d2a..191045a 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -220,6 +220,9 @@ static struct pci_controller pci2_hose;
int first_free_busno = 0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
@@ -231,8 +234,8 @@ void pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
>> MPC8641_PORBMSR_HA_SHIFT;
@@ -251,27 +254,23 @@ void pci_init_board(void)
debug("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -293,32 +292,28 @@ void pci_init_board(void)
#ifdef CONFIG_PCI2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
+ struct pci_region *r = hose->regions;
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BASE,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@@ -337,33 +332,19 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
-void
-ft_board_setup (void *blob, bd_t *bd)
+void ft_board_setup (void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
- }
}
#endif
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 0492274..fe80e5d 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -279,11 +279,6 @@
#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
/* For RTL8139 */
#define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); })
#define _IO_BASE 0x00000000
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index ceb2c69..80c8bee 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -305,11 +305,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
/* For RTL8139 */
#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
#define _IO_BASE 0x00000000
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 14d1c88..09a9901 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -308,11 +308,6 @@
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup
2008-10-23 6:26 [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 01/10] pci: Allow for PCI addresses to be 64-bit Kumar Gala
@ 2008-10-23 8:35 ` Wolfgang Denk
2008-10-23 11:58 ` Kumar Gala
1 sibling, 1 reply; 20+ messages in thread
From: Wolfgang Denk @ 2008-10-23 8:35 UTC (permalink / raw)
To: u-boot
Dear Kumar Gala,
In message <1224743208-11160-1-git-send-email-galak@kernel.crashing.org> you wrote:
> This patch series adds the ability to support 64-bit PCI addresses as well
> as refactors the fsl_pci_init code and cleans up its users.
>
> Finally it adds some help functions that the board code calls to set
> dma-ranges in device trees.
>
> If the particular maintainers could ack the patches that would be great
> (Andy, Jon, Jerry).
So who is supposed to apply the patches, then? Me?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Security is mostly a superstition. It does not exist in nature...
Life is either a daring adventure or nothing." - Helen Keller
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers
2008-10-23 6:26 ` [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 05/10] fdt: Added helper to set PCI dma-ranges property Kumar Gala
@ 2008-10-23 11:55 ` Jerry Van Baren
2008-10-23 12:04 ` Kumar Gala
1 sibling, 1 reply; 20+ messages in thread
From: Jerry Van Baren @ 2008-10-23 11:55 UTC (permalink / raw)
To: u-boot
Kumar Gala wrote:
> Add helper functions to return top level #size-cell and #address-cell info
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> include/fdt_support.h | 18 ++++++++++++++++++
> 1 files changed, 18 insertions(+), 0 deletions(-)
>
> diff --git a/include/fdt_support.h b/include/fdt_support.h
> index ceaadc2..aa9d86b 100644
> --- a/include/fdt_support.h
> +++ b/include/fdt_support.h
> @@ -28,6 +28,24 @@
>
> #include <fdt.h>
>
> +static inline int fdt_addrcell(void *blob) {
> + const u32 *addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
> +
> + if (addrcell)
> + return *addrcell;
> + else
> + return 1;
> +}
> +
> +static inline int fdt_sizecell(void *blob) {
> + const u32 *sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
> +
> + if (sizecell)
> + return *sizecell;
> + else
> + return 1;
> +}
> +
> int fdt_chosen(void *fdt, int force);
> int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
> void do_fixup_by_path(void *fdt, const char *path, const char *prop,
Hi Kumar,
What about collapsing the two above into a common function?
fdt_addrcell(blob);
becomes
fdt_get_prop_u32(blob, "/", "#address-cells", 1);
and
fdt_sizecell(blob);
becomes
fdt_get_prop_u32(blob, "/", "#size-cells", 1);
WARNING, UNTESTED CODE:
/**
* fdt_get_prop_u32: Find a node and return it's property or a default
*
* @fdt: ptr to device tree
* @node: path of node
* @prop: property name
* @defalt: default value if the property isn't found
*
* Convenience function to find a node and return it's property or a
* default value if it doesn't exist.
*/
u32 fdt_get_prop_u32(void *fdt, const char *node, const char *prop,
const u32 default)
{
const u32 *addrcell = fdt_getprop(fdt, node, prop, NULL);
if (addrcell)
return *addrcell;
else
return default;
}
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup
2008-10-23 8:35 ` [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup Wolfgang Denk
@ 2008-10-23 11:58 ` Kumar Gala
2008-10-24 22:48 ` Andy Fleming
0 siblings, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 11:58 UTC (permalink / raw)
To: u-boot
On Oct 23, 2008, at 3:35 AM, Wolfgang Denk wrote:
> Dear Kumar Gala,
>
> In message <1224743208-11160-1-git-send-email-galak@kernel.crashing.org
> > you wrote:
>> This patch series adds the ability to support 64-bit PCI addresses
>> as well
>> as refactors the fsl_pci_init code and cleans up its users.
>>
>> Finally it adds some help functions that the board code calls to set
>> dma-ranges in device trees.
>>
>> If the particular maintainers could ack the patches that would be
>> great
>> (Andy, Jon, Jerry).
>
> So who is supposed to apply the patches, then? Me?
yes :)
I practice Andy can apply them to u-boot-85xx if you ack the first
patch and Jerry ack's the fdt patches.
- k
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers
2008-10-23 11:55 ` [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers Jerry Van Baren
@ 2008-10-23 12:04 ` Kumar Gala
2008-10-23 12:26 ` Jerry Van Baren
0 siblings, 1 reply; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 12:04 UTC (permalink / raw)
To: u-boot
On Oct 23, 2008, at 6:55 AM, Jerry Van Baren wrote:
> Kumar Gala wrote:
>> Add helper functions to return top level #size-cell and #address-
>> cell info
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> ---
>> include/fdt_support.h | 18 ++++++++++++++++++
>> 1 files changed, 18 insertions(+), 0 deletions(-)
>> diff --git a/include/fdt_support.h b/include/fdt_support.h
>> index ceaadc2..aa9d86b 100644
>> --- a/include/fdt_support.h
>> +++ b/include/fdt_support.h
>> @@ -28,6 +28,24 @@
>> #include <fdt.h>
>> +static inline int fdt_addrcell(void *blob) {
>> + const u32 *addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
>> +
>> + if (addrcell)
>> + return *addrcell;
>> + else
>> + return 1;
>> +}
>> +
>> +static inline int fdt_sizecell(void *blob) {
>> + const u32 *sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
>> +
>> + if (sizecell)
>> + return *sizecell;
>> + else
>> + return 1;
>> +}
>> +
>> int fdt_chosen(void *fdt, int force);
>> int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int
>> force);
>> void do_fixup_by_path(void *fdt, const char *path, const char *prop,
>
> Hi Kumar,
>
> What about collapsing the two above into a common function?
>
> fdt_addrcell(blob);
> becomes
> fdt_get_prop_u32(blob, "/", "#address-cells", 1);
> and
> fdt_sizecell(blob);
> becomes
> fdt_get_prop_u32(blob, "/", "#size-cells", 1);
>
> WARNING, UNTESTED CODE:
> /**
> * fdt_get_prop_u32: Find a node and return it's property or a default
> *
> * @fdt: ptr to device tree
> * @node: path of node
> * @prop: property name
> * @defalt: default value if the property isn't found
> *
> * Convenience function to find a node and return it's property or a
> * default value if it doesn't exist.
> */
> u32 fdt_get_prop_u32(void *fdt, const char *node, const char *prop,
> const u32 default)
> {
> const u32 *addrcell = fdt_getprop(fdt, node, prop, NULL);
>
> if (addrcell)
> return *addrcell;
> else
> return default;
> }
I'd prefer we call it fdt_getprop_u32_default(). If you are good with
the name I'll change my patchset.
- k
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers
2008-10-23 12:04 ` Kumar Gala
@ 2008-10-23 12:26 ` Jerry Van Baren
2008-10-23 12:59 ` Kumar Gala
0 siblings, 1 reply; 20+ messages in thread
From: Jerry Van Baren @ 2008-10-23 12:26 UTC (permalink / raw)
To: u-boot
Kumar Gala wrote:
>
> On Oct 23, 2008, at 6:55 AM, Jerry Van Baren wrote:
>
>> Kumar Gala wrote:
>>> Add helper functions to return top level #size-cell and #address-cell
>>> info
>>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>>> ---
>>> include/fdt_support.h | 18 ++++++++++++++++++
>>> 1 files changed, 18 insertions(+), 0 deletions(-)
>>> diff --git a/include/fdt_support.h b/include/fdt_support.h
>>> index ceaadc2..aa9d86b 100644
>>> --- a/include/fdt_support.h
>>> +++ b/include/fdt_support.h
>>> @@ -28,6 +28,24 @@
>>> #include <fdt.h>
>>> +static inline int fdt_addrcell(void *blob) {
>>> + const u32 *addrcell = fdt_getprop(blob, 0, "#address-cells", NULL);
>>> +
>>> + if (addrcell)
>>> + return *addrcell;
>>> + else
>>> + return 1;
>>> +}
>>> +
>>> +static inline int fdt_sizecell(void *blob) {
>>> + const u32 *sizecell = fdt_getprop(blob, 0, "#size-cells", NULL);
>>> +
>>> + if (sizecell)
>>> + return *sizecell;
>>> + else
>>> + return 1;
>>> +}
>>> +
>>> int fdt_chosen(void *fdt, int force);
>>> int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int
>>> force);
>>> void do_fixup_by_path(void *fdt, const char *path, const char *prop,
>>
>> Hi Kumar,
>>
>> What about collapsing the two above into a common function?
>>
>> fdt_addrcell(blob);
>> becomes
>> fdt_get_prop_u32(blob, "/", "#address-cells", 1);
>> and
>> fdt_sizecell(blob);
>> becomes
>> fdt_get_prop_u32(blob, "/", "#size-cells", 1);
>>
>> WARNING, UNTESTED CODE:
>> /**
>> * fdt_get_prop_u32: Find a node and return it's property or a default
>> *
>> * @fdt: ptr to device tree
>> * @node: path of node
>> * @prop: property name
>> * @defalt: default value if the property isn't found
>> *
>> * Convenience function to find a node and return it's property or a
>> * default value if it doesn't exist.
>> */
>> u32 fdt_get_prop_u32(void *fdt, const char *node, const char *prop,
>> const u32 default)
>> {
>> const u32 *addrcell = fdt_getprop(fdt, node, prop, NULL);
>>
>> if (addrcell)
>> return *addrcell;
>> else
>> return default;
>> }
>
> I'd prefer we call it fdt_getprop_u32_default(). If you are good with
> the name I'll change my patchset.
>
> - k
That was my second choice. I figured Dennis Richie would call me up and
complain the name was too long. ;-)
I'm find with the change.
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Thanks,
gvb
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers
2008-10-23 12:26 ` Jerry Van Baren
@ 2008-10-23 12:59 ` Kumar Gala
0 siblings, 0 replies; 20+ messages in thread
From: Kumar Gala @ 2008-10-23 12:59 UTC (permalink / raw)
To: u-boot
>>>>
>>>
>>> Hi Kumar,
>>>
>>> What about collapsing the two above into a common function?
>>>
>>> fdt_addrcell(blob);
>>> becomes
>>> fdt_get_prop_u32(blob, "/", "#address-cells", 1);
>>> and
>>> fdt_sizecell(blob);
>>> becomes
>>> fdt_get_prop_u32(blob, "/", "#size-cells", 1);
>>>
>>> WARNING, UNTESTED CODE:
>>> /**
>>> * fdt_get_prop_u32: Find a node and return it's property or a
>>> default
>>> *
>>> * @fdt: ptr to device tree
>>> * @node: path of node
>>> * @prop: property name
>>> * @defalt: default value if the property isn't found
>>> *
>>> * Convenience function to find a node and return it's property or a
>>> * default value if it doesn't exist.
>>> */
>>> u32 fdt_get_prop_u32(void *fdt, const char *node, const char *prop,
>>> const u32 default)
>>> {
>>> const u32 *addrcell = fdt_getprop(fdt, node, prop, NULL);
>>>
>>> if (addrcell)
>>> return *addrcell;
>>> else
>>> return default;
>>> }
>> I'd prefer we call it fdt_getprop_u32_default(). If you are good
>> with the name I'll change my patchset.
>> - k
>
> That was my second choice. I figured Dennis Richie would call me up
> and complain the name was too long. ;-)
>
> I'm find with the change.
>
> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
>
> Thanks,
> gvb
sent two new patches for you to ack.
- k
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 10/10] 86xx: Convert all fsl_pci_init users to new APIs
2008-10-23 6:26 ` [U-Boot] [PATCH 10/10] 86xx: " Kumar Gala
@ 2008-10-24 0:41 ` Jon Loeliger
0 siblings, 0 replies; 20+ messages in thread
From: Jon Loeliger @ 2008-10-24 0:41 UTC (permalink / raw)
To: u-boot
> Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use
> fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup().
>
> With these changes the board code is a bit smaller and we get dma-ranges
> set in the device tree for these boards.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
ACK.
jdl
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 01/10] pci: Allow for PCI addresses to be 64-bit
2008-10-23 6:26 ` [U-Boot] [PATCH 01/10] pci: Allow for PCI addresses to be 64-bit Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 02/10] 85xx: Enable 64-bit PCI resources on all Freescale boards Kumar Gala
@ 2008-10-24 13:12 ` Wolfgang Denk
1 sibling, 0 replies; 20+ messages in thread
From: Wolfgang Denk @ 2008-10-24 13:12 UTC (permalink / raw)
To: u-boot
Dear Kumar Gala,
In message <1224743208-11160-2-git-send-email-galak@kernel.crashing.org> you wrote:
> PCI bus is inherently 64-bit. While not all system require access to
> the full 64-bit PCI address range some do. This allows those systems
> to enable the full PCI address width via CONFIG_SYS_PCI_64BIT.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> drivers/pci/pci.c | 37 ++++++++++++++------
> drivers/pci/pci_auto.c | 88 ++++++++++++++++++++++++++++-------------------
> include/pci.h | 40 +++++++++++++---------
> 3 files changed, 102 insertions(+), 63 deletions(-)
Acked-by: Wolfgang Denk <wd@denx.de>
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Half of the people in the world are below average.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup
2008-10-23 11:58 ` Kumar Gala
@ 2008-10-24 22:48 ` Andy Fleming
0 siblings, 0 replies; 20+ messages in thread
From: Andy Fleming @ 2008-10-24 22:48 UTC (permalink / raw)
To: u-boot
And thus have I done so. 1-10 applied, thanks
Andy
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2008-10-24 22:48 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-10-23 6:26 [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 01/10] pci: Allow for PCI addresses to be 64-bit Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 02/10] 85xx: Enable 64-bit PCI resources on all Freescale boards Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 03/10] 86xx: " Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 05/10] fdt: Added helper to set PCI dma-ranges property Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 06/10] pci/fsl_pci_init: Enable larger address and setting inbound windows properly Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 07/10] pci/fsl_pci_init: Add a common PCI inbound setup function Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 08/10] pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-ranges Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 09/10] 85xx: Convert all fsl_pci_init users to new APIs Kumar Gala
2008-10-23 6:26 ` [U-Boot] [PATCH 10/10] 86xx: " Kumar Gala
2008-10-24 0:41 ` Jon Loeliger
2008-10-23 11:55 ` [U-Boot] [PATCH 04/10] fdt: Add fdt_sizecell & fdt_addrcell helpers Jerry Van Baren
2008-10-23 12:04 ` Kumar Gala
2008-10-23 12:26 ` Jerry Van Baren
2008-10-23 12:59 ` Kumar Gala
2008-10-24 13:12 ` [U-Boot] [PATCH 01/10] pci: Allow for PCI addresses to be 64-bit Wolfgang Denk
2008-10-23 8:35 ` [U-Boot] [PATCH 00/10] 85xx/85xx pci cleanup Wolfgang Denk
2008-10-23 11:58 ` Kumar Gala
2008-10-24 22:48 ` Andy Fleming
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