[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Ian Campbell]

Hi,

This is my first cut at an upstreamable series based upon the
https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
intention is to present a minimal starting point for upstreaming to
which support for other processors, peripherals, boards etc can be
added in the future. Therefore this has been stripped right back and
currently supports only sun7i processors and the cubietruck
board. Supported peripherals are UART, MMC and Ethernet.

The code here is from sunxi.git#sunxi[0] changeset d854c4de2f57 "arm:
Handle .gnu.hash section in ldscripts" and applied to u-boot v2014.01.

This series can also be found at:

    git://gitorious.org/ijc/u-boot.git sunxi-mainlining-v1

There is no SMP here, since that relies on the PSCI support from Marc
Zyngier which has yet to land in mainline AFAIK.

I've tried to give corect credit and S-o-b based upon:
  git log --pretty='%aN' linux-sunxi/sunxi -- [PATHS] | sort -u
  git log linux-sunxi/sunxi -- [PATHS] | grep -i signed.off.by  | sort -u
  Manual inspection

This will tend to over credit, since it will include folks who
contributed code which has since been removed as well as those who
contributed code which is not included in this patch set, but I think
it is better to be conservative and include too many rather than
incorrectly exclude people. Doing better than this would be IMHO too
hard to be worth it (e.g. git blame would prefer a recent whitespace
cleanup to the actual author of the code and prefer someone did code
motion over the original author, so it would be a massive & manual
process).

I considered using the sunxi.git#sunxi-patchqueue branch but it was
151 patches and there didn't seem to be a small enough set of prefix
patches which I was comfortable starting from.

Cheers,
Ian.

[0] https://github.com/linux-sunxi/u-boot-sunxi.git

[U-Boot] [PATCH v1 1/9] sunxi: initial sun7i clocks and timer support.

[Ian Campbell]

Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
ldscripts" vs v2014.01.

This has been stripped back for mainlining and supports only sun7i. These
changes are not useful by themselves but are split out to make the patch sizes
more manageable.

As well as the following signed-off-by the sunxi branch shows commits to these
files authored by the following:
  Alejandro Mery
  Carl van Schaik
  Stefan Roese
  Tom Cubie
  yemao

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>

---
Contributors:
  git log --pretty='%aN' linux-sunxi/sunxi -- [PATHS] | sort -u
---
 arch/arm/cpu/armv7/sunxi/Makefile           |  28 ++++
 arch/arm/cpu/armv7/sunxi/clock.c            | 177 +++++++++++++++++++++
 arch/arm/cpu/armv7/sunxi/timer.c            | 120 ++++++++++++++
 arch/arm/include/asm/arch-sunxi/clock.h     | 238 ++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/sys_proto.h |  33 ++++
 arch/arm/include/asm/arch-sunxi/timer.h     | 104 ++++++++++++
 6 files changed, 700 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/Makefile
 create mode 100644 arch/arm/cpu/armv7/sunxi/clock.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/timer.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/clock.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/sys_proto.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/timer.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
new file mode 100644
index 0000000..b56c32b
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+#
+# Based on some other Makefile
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+obj-y	+= timer.o
+obj-y	+= clock.o
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
new file mode 100644
index 0000000..e3abaf0
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+static void clock_init_safe(void)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* Set safe defaults until PMU is configured */
+	writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
+	       CPU_CLK_SRC_OSC24M << 16, &ccm->cpu_ahb_apb0_cfg);
+	writel(0xa1005000, &ccm->pll1_cfg);
+	sdelay(200);
+	writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
+	       CPU_CLK_SRC_PLL1 << 16, &ccm->cpu_ahb_apb0_cfg);
+	writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
+	writel(0x1 << 31 | readl(&ccm->pll6_cfg), &ccm->pll6_cfg);
+}
+#endif
+
+int clock_init(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+#ifdef CONFIG_SPL_BUILD
+	clock_init_safe();
+#endif
+
+	/* uart clock source is apb1 */
+	sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
+	sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N);
+	sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M);
+
+	/* open the clock for uart */
+	sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
+
+	return 0;
+}
+
+/* Return PLL5 frequency in Hz
+ * Note: Assumes PLL5 reference is 24MHz clock
+ */
+unsigned int clock_get_pll5(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	uint32_t rval = readl(&ccm->pll5_cfg);
+	int n = (rval >> 8) & 0x1f;
+	int k = ((rval >> 4) & 3) + 1;
+	int p = 1 << ((rval >> 16) & 3);
+	return 24000000 * n * k / p;
+}
+
+int clock_twi_onoff(int port, int state)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	if (port > 2)
+		return -1;
+
+	/* set the apb1 clock gate for twi */
+	sr32(&ccm->apb1_gate, 0 + port, 1, state);
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#define PLL1_CFG(N, K, M, P)	(1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | \
+				 16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \
+				 (K) << 4 | 0 << 3 | 0 << 2 | (M) << 0)
+#define RDIV(a, b)		((a + (b) - 1) / (b))
+
+struct {
+	u32 pll1_cfg;
+	unsigned int freq;
+} pll1_para[] = {
+	{ PLL1_CFG(16, 0, 0, 0), 384000000 },
+	{ PLL1_CFG(16, 1, 0, 0), 768000000 },
+	{ PLL1_CFG(20, 1, 0, 0), 960000000 },
+	{ PLL1_CFG(21, 1, 0, 0), 1008000000},
+	{ PLL1_CFG(22, 1, 0, 0), 1056000000},
+	{ PLL1_CFG(23, 1, 0, 0), 1104000000},
+	{ PLL1_CFG(24, 1, 0, 0), 1152000000},
+	{ PLL1_CFG(25, 1, 0, 0), 1200000000},
+	{ PLL1_CFG(26, 1, 0, 0), 1248000000},
+	{ PLL1_CFG(27, 1, 0, 0), 1296000000},
+	{ PLL1_CFG(28, 1, 0, 0), 1344000000},
+	{ PLL1_CFG(29, 1, 0, 0), 1392000000},
+	{ PLL1_CFG(30, 1, 0, 0), 1440000000},
+	{ PLL1_CFG(31, 1, 0, 0), 1488000000},
+	{ PLL1_CFG(31, 1, 0, 0), ~0},
+};
+
+void clock_set_pll1(int hz)
+{
+	int i = 0;
+	int axi, ahb, apb0;
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* Find target frequency */
+	while (pll1_para[i].freq < hz)
+		i++;
+
+	hz = pll1_para[i].freq;
+
+	/* Calculate system clock divisors */
+	axi = RDIV(hz, 432000000);		/* Max 450MHz */
+	ahb = RDIV(hz/axi, 204000000);		/* Max 250MHz */
+	apb0 = 2;				/* Max 150MHz */
+
+	printf("CPU: %dHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
+
+	/* Map divisors to register values */
+	axi = axi - 1;
+	if (ahb > 4)
+		ahb = 3;
+	else if (ahb > 2)
+		ahb = 2;
+	else if (ahb > 1)
+		ahb = 1;
+	else
+		ahb = 0;
+
+	apb0 = apb0 - 1;
+
+	/* Switch to 24MHz clock while changing PLL1 */
+	writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
+	       CPU_CLK_SRC_OSC24M << 16, &ccm->cpu_ahb_apb0_cfg);
+	sdelay(20);
+
+	/* Configure sys clock divisors */
+	writel(axi << 0 | ahb << 4 | apb0 << 8 | CPU_CLK_SRC_OSC24M << 16,
+	       &ccm->cpu_ahb_apb0_cfg);
+
+	/* Configure PLL1 at the desired frequency */
+	writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
+	sdelay(200);
+
+	/* Switch CPU to PLL1 */
+	writel(axi << 0 | ahb << 4 | apb0 << 8 | CPU_CLK_SRC_PLL1 << 16,
+	       &ccm->cpu_ahb_apb0_cfg);
+	sdelay(20);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/timer.c b/arch/arm/cpu/armv7/sunxi/timer.c
new file mode 100644
index 0000000..c69ed73
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/timer.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_MODE   (0x0 << 7)	/* continuous mode */
+#define TIMER_DIV    (0x0 << 4)	/* pre scale 1 */
+#define TIMER_SRC    (0x1 << 2)	/* osc24m */
+#define TIMER_RELOAD (0x1 << 1)	/* reload internal value */
+#define TIMER_EN     (0x1 << 0)	/* enable timer */
+
+#define TIMER_CLOCK		(24 * 1000 * 1000)
+#define COUNT_TO_USEC(x)	((x) / 24)
+#define USEC_TO_COUNT(x)	((x) * 24)
+#define TICKS_PER_HZ		(TIMER_CLOCK / CONFIG_SYS_HZ)
+#define TICKS_TO_HZ(x)		((x) / TICKS_PER_HZ)
+
+#define TIMER_LOAD_VAL		0xffffffff
+
+#define TIMER_NUM		0	/* we use timer 0 */
+
+static struct sunxi_timer *timer_base =
+	&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->timer[TIMER_NUM];
+
+/* macro to read the 32 bit timer: since it decrements, we invert read value */
+#define READ_TIMER() (~readl(&timer_base->val))
+
+/* init timer register */
+int timer_init(void)
+{
+	writel(TIMER_LOAD_VAL, &timer_base->inter);
+	writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
+	       &timer_base->ctl);
+
+	return 0;
+}
+
+/* timer without interrupts */
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = TICKS_TO_HZ(READ_TIMER());
+
+	if (now >= gd->arch.lastinc)	/* normal (non rollover) */
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	else {
+		/* rollover */
+		gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
+				- gd->arch.lastinc) + now;
+	}
+	gd->arch.lastinc = now;
+
+	return gd->arch.tbl;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+	long tmo = USEC_TO_COUNT(usec);
+	ulong now, last = READ_TIMER();
+
+	while (tmo > 0) {
+		now = READ_TIMER();
+		if (now > last)	/* normal (non rollover) */
+			tmo -= now - last;
+		else		/* rollover */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
new file mode 100644
index 0000000..af824dc
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SUNXI_CLOCK_H
+#define _SUNXI_CLOCK_H
+
+#include <linux/types.h>
+
+/* clock control module regs definition */
+
+struct sunxi_ccm_reg {
+	u32 pll1_cfg;		/* 0x00 pll1 control */
+	u32 pll1_tun;		/* 0x04 pll1 tuning */
+	u32 pll2_cfg;		/* 0x08 pll2 control */
+	u32 pll2_tun;		/* 0x0c pll2 tuning */
+	u32 pll3_cfg;		/* 0x10 pll3 control */
+	u8 res0[0x4];
+	u32 pll4_cfg;		/* 0x18 pll4 control */
+	u8 res1[0x4];
+	u32 pll5_cfg;		/* 0x20 pll5 control */
+	u32 pll5_tun;		/* 0x24 pll5 tuning */
+	u32 pll6_cfg;		/* 0x28 pll6 control */
+	u32 pll6_tun;		/* 0x2c pll6 tuning */
+	u32 pll7_cfg;		/* 0x30 pll7 control */
+	u32 pll1_tun2;		/* 0x34 pll5 tuning2 */
+	u8 res2[0x4];
+	u32 pll5_tun2;		/* 0x3c pll5 tuning2 */
+	u8 res3[0xc];
+	u32 pll_lock_dbg;	/* 0x4c pll lock time debug */
+	u32 osc24m_cfg;		/* 0x50 osc24m control */
+	u32 cpu_ahb_apb0_cfg;	/* 0x54 cpu,ahb and apb0 divide ratio */
+	u32 apb1_clk_div_cfg;	/* 0x58 apb1 clock dividor */
+	u32 axi_gate;		/* 0x5c axi module clock gating */
+	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
+	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
+	u32 apb0_gate;		/* 0x68 apb0 module clock gating */
+	u32 apb1_gate;		/* 0x6c apb1 module clock gating */
+	u8 res4[0x10];
+	u32 nand_sclk_cfg;	/* 0x80 nand sub clock control */
+	u32 ms_sclk_cfg;	/* 0x84 memory stick sub clock control */
+	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
+	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
+	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
+	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
+	u32 ts_clk_cfg;		/* 0x98 transport stream clock control */
+	u32 ss_clk_cfg;		/* 0x9c */
+	u32 spi0_clk_cfg;	/* 0xa0 */
+	u32 spi1_clk_cfg;	/* 0xa4 */
+	u32 spi2_clk_cfg;	/* 0xa8 */
+	u32 pata_clk_cfg;	/* 0xac */
+	u32 ir0_clk_cfg;	/* 0xb0 */
+	u32 ir1_clk_cfg;	/* 0xb4 */
+	u32 iis_clk_cfg;	/* 0xb8 */
+	u32 ac97_clk_cfg;	/* 0xbc */
+	u32 spdif_clk_cfg;	/* 0xc0 */
+	u32 keypad_clk_cfg;	/* 0xc4 */
+	u32 sata_clk_cfg;	/* 0xc8 */
+	u32 usb_clk_cfg;	/* 0xcc */
+	u32 gps_clk_cfg;	/* 0xd0 */
+	u32 spi3_clk_cfg;	/* 0xd4 */
+	u8 res5[0x28];
+	u32 dram_clk_cfg;	/* 0x100 */
+	u32 be0_clk_cfg;	/* 0x104 */
+	u32 be1_clk_cfg;	/* 0x108 */
+	u32 fe0_clk_cfg;	/* 0x10c */
+	u32 fe1_clk_cfg;	/* 0x110 */
+	u32 mp_clk_cfg;		/* 0x114 */
+	u32 lcd0_ch0_clk_cfg;	/* 0x118 */
+	u32 lcd1_ch0_clk_cfg;	/* 0x11c */
+	u32 csi_isp_clk_cfg;	/* 0x120 */
+	u8 res6[0x4];
+	u32 tvd_clk_reg;	/* 0x128 */
+	u32 lcd0_ch1_clk_cfg;	/* 0x12c */
+	u32 lcd1_ch1_clk_cfg;	/* 0x130 */
+	u32 csi0_clk_cfg;	/* 0x134 */
+	u32 csi1_clk_cfg;	/* 0x138 */
+	u32 ve_clk_cfg;		/* 0x13c */
+	u32 audio_codec_clk_cfg;	/* 0x140 */
+	u32 avs_clk_cfg;	/* 0x144 */
+	u32 ace_clk_cfg;	/* 0x148 */
+	u32 lvds_clk_cfg;	/* 0x14c */
+	u32 hdmi_clk_cfg;	/* 0x150 */
+	u32 mali_clk_cfg;	/* 0x154 */
+	u8 res7[0x4];
+	u32 mbus_clk_cfg;	/* 0x15c */
+	u8 res8[0x4];
+	u32 gmac_clk_cfg;	/* 0x164 */
+};
+
+/* apb1 bit field */
+#define APB1_CLK_SRC_OSC24M		0
+#define APB1_FACTOR_M			0
+#define APB1_FACTOR_N			0
+
+/* clock divide */
+#define CPU_CLK_SRC_OSC24M		1
+#define CPU_CLK_SRC_PLL1		2
+#define AXI_DIV_1			0
+#define AXI_DIV_2			1
+#define AXI_DIV_3			2
+#define AXI_DIV_4			3
+#define AHB_DIV_1			0
+#define AHB_DIV_2			1
+#define AHB_DIV_4			2
+#define AHB_DIV_8			3
+#define APB0_DIV_1			0
+#define APB0_DIV_2			1
+#define APB0_DIV_4			2
+#define APB0_DIV_8			3
+
+#define CLK_GATE_OPEN			0x1
+#define CLK_GATE_CLOSE			0x0
+
+/* nand clock */
+#define NAND_CLK_SRC_OSC24		0
+#define NAND_CLK_DIV_N			0
+#define NAND_CLK_DIV_M			0
+
+/* gps clock */
+#define GPS_SCLK_GATING_OFF		0
+#define GPS_RESET			0
+
+/* ahb clock gate bit offset */
+#define AHB_GATE_OFFSET_GPS		26
+#define AHB_GATE_OFFSET_SATA		25
+#define AHB_GATE_OFFSET_PATA		24
+#define AHB_GATE_OFFSET_SPI3		23
+#define AHB_GATE_OFFSET_SPI2		22
+#define AHB_GATE_OFFSET_SPI1		21
+#define AHB_GATE_OFFSET_SPI0		20
+#define AHB_GATE_OFFSET_TS0		18
+#define AHB_GATE_OFFSET_EMAC		17
+#define AHB_GATE_OFFSET_ACE		16
+#define AHB_GATE_OFFSET_DLL		15
+#define AHB_GATE_OFFSET_SDRAM		14
+#define AHB_GATE_OFFSET_NAND		13
+#define AHB_GATE_OFFSET_MS		12
+#define AHB_GATE_OFFSET_MMC3		11
+#define AHB_GATE_OFFSET_MMC2		10
+#define AHB_GATE_OFFSET_MMC1		9
+#define AHB_GATE_OFFSET_MMC0		8
+#define AHB_GATE_OFFSET_BIST		7
+#define AHB_GATE_OFFSET_DMA		6
+#define AHB_GATE_OFFSET_SS		5
+#define AHB_GATE_OFFSET_USB_OHCI1	4
+#define AHB_GATE_OFFSET_USB_EHCI1	3
+#define AHB_GATE_OFFSET_USB_OHCI0	2
+#define AHB_GATE_OFFSET_USB_EHCI0	1
+#define AHB_GATE_OFFSET_USB		0
+
+/* ahb clock gate bit offset (second register) */
+#define AHB_GATE_OFFSET_GMAC		17
+
+#define CCM_AHB_GATE_GPS (0x1 << 26)
+#define CCM_AHB_GATE_SDRAM (0x1 << 14)
+#define CCM_AHB_GATE_DLL (0x1 << 15)
+#define CCM_AHB_GATE_ACE (0x1 << 16)
+
+#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
+#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
+#define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2)
+#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
+#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
+#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
+#define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_LDO (0x1 << 7)
+#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
+#define CCM_PLL5_CTRL_N_X(n) (n)
+#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
+#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
+#define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_BW (0x1 << 18)
+#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19)
+#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20)
+#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f)
+#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25)
+#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29)
+#define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
+#define CCM_PLL5_CTRL_EN (0x1 << 31)
+
+#define CCM_GPS_CTRL_RESET (0x1 << 0)
+#define CCM_GPS_CTRL_GATE (0x1 << 1)
+
+#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15)
+
+#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0)
+#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf)
+#define CCM_MBUS_CTRL_M_X(n) ((n) - 1)
+#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16)
+#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf)
+#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0)))
+#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24)
+#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3)
+#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0
+#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1
+#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
+#define CCM_MBUS_CTRL_GATE (0x1 << 31)
+
+#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
+#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
+#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
+#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
+#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+
+
+#ifndef __ASSEMBLY__
+int clock_init(void);
+int clock_twi_onoff(int port, int state);
+void clock_set_pll1(int mhz);
+unsigned int clock_get_pll5(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
new file mode 100644
index 0000000..78a2b39
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <linux/types.h>
+
+void sr32(u32 *, u32, u32, u32);
+void sdelay(unsigned long);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
new file mode 100644
index 0000000..f9d4f4f
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Configuration settings for the Allwinner A10-evb board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SUNXI_TIMER_H_
+#define _SUNXI_TIMER_H_
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+/* General purpose timer */
+struct sunxi_timer {
+	u32 ctl;
+	u32 inter;
+	u32 val;
+	u8 res[4];
+};
+
+/* Audio video sync*/
+struct sunxi_avs {
+	u32 ctl;		/* 0x80 */
+	u32 cnt0;		/* 0x84 */
+	u32 cnt1;		/* 0x88 */
+	u32 div;		/* 0x8c */
+};
+
+/* 64 bit counter */
+struct sunxi_64cnt {
+	u32 ctl;		/* 0xa0 */
+	u32 lo;			/* 0xa4 */
+	u32 hi;			/* 0xa8 */
+};
+
+/* Watchdog */
+struct sunxi_wdog {
+	u32 ctl;		/* 0x90 */
+	u32 mode;		/* 0x94 */
+};
+
+/* Rtc */
+struct sunxi_rtc {
+	u32 ctl;		/* 0x100 */
+	u32 yymmdd;		/* 0x104 */
+	u32 hhmmss;		/* 0x108 */
+};
+
+/* Alarm */
+struct sunxi_alarm {
+	u32 ddhhmmss;		/* 0x10c */
+	u32 hhmmss;		/* 0x110 */
+	u32 en;			/* 0x114 */
+	u32 irqen;		/* 0x118 */
+	u32 irqsta;		/* 0x11c */
+};
+
+/* Timer general purpose register */
+struct sunxi_tgp {
+	u32 tgpd;
+};
+
+struct sunxi_timer_reg {
+	u32 tirqen;		/* 0x00 */
+	u32 tirqsta;		/* 0x04 */
+	u8 res1[8];
+	struct sunxi_timer timer[6];	/* We have 6 timers */
+	u8 res2[16];
+	struct sunxi_avs avs;
+	struct sunxi_wdog wdog;
+	u8 res3[8];
+	struct sunxi_64cnt cnt64;
+	u8 res4[0x58];
+	struct sunxi_rtc rtc;
+	struct sunxi_alarm alarm;
+	struct sunxi_tgp tgp[4];
+	u8 res5[8];
+	u32 cpu_cfg;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif
-- 
1.8.5.3

[U-Boot] [PATCH v1 1/9] sunxi: initial sun7i clocks and timer support.

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:43AM +0000, Ian Campbell wrote:

[snip]
> +	writel(0xa1005000, &ccm->pll1_cfg);
> +	sdelay(200);
> +	writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
> +	       CPU_CLK_SRC_PLL1 << 16, &ccm->cpu_ahb_apb0_cfg);
> +	writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
> +	writel(0x1 << 31 | readl(&ccm->pll6_cfg), &ccm->pll6_cfg);

All magic bits and shifts need defining.

> +/*
> + * This function is derived from PowerPC code (timebase clock frequency).
> + * On ARM it returns the number of timer ticks per second.
> + */
> +ulong get_tbclk(void)
> +{
> +	ulong tbclk;
> +	tbclk = CONFIG_SYS_HZ;
> +	return tbclk;
> +}

So, just return CONFIG_SYS_HZ ?

-- 
Tom
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[U-Boot] [PATCH v1 2/9] sunxi: initial sun7i pinmux and gpio support

[Ian Campbell]

Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
ldscripts" vs v2014.01.

This has been stripped back for mainlining and supports only sun7i. These
changes are not useful by themselves but are split out to make the patch sizes
more manageable.

As well as the following signed-off-by the sunxi branch shows commits to these
files authored by the following:
  Carl van Schaik
  Henrik Nordstrom
  Stefan Roese
  Tom Cubie

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/sunxi/Makefile      |   1 +
 arch/arm/cpu/armv7/sunxi/pinmux.c      |  96 ++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/gpio.h | 179 +++++++++++++++++++++++++++++++++
 3 files changed, 276 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/pinmux.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/gpio.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index b56c32b..b4298c0 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -26,3 +26,4 @@
 
 obj-y	+= timer.o
 obj-y	+= clock.o
+obj-y	+= pinmux.o
diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c
new file mode 100644
index 0000000..56671f6
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/pinmux.c
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+{
+	u32 cfg;
+	u32 bank = GPIO_BANK(pin);
+	u32 index = GPIO_CFG_INDEX(pin);
+	u32 offset = GPIO_CFG_OFFSET(pin);
+	struct sunxi_gpio *pio =
+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+
+	cfg = readl(&pio->cfg[0] + index);
+	cfg &= ~(0xf << offset);
+	cfg |= val << offset;
+
+	writel(cfg, &pio->cfg[0] + index);
+
+	return 0;
+}
+
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+	u32 cfg;
+	u32 bank = GPIO_BANK(pin);
+	u32 index = GPIO_CFG_INDEX(pin);
+	u32 offset = GPIO_CFG_OFFSET(pin);
+	struct sunxi_gpio *pio =
+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+
+	cfg = readl(&pio->cfg[0] + index);
+	cfg >>= offset;
+
+	return cfg & 0xf;
+}
+
+int sunxi_gpio_set_drv(u32 pin, u32 val)
+{
+	u32 drv;
+	u32 bank = GPIO_BANK(pin);
+	u32 index = GPIO_DRV_INDEX(pin);
+	u32 offset = GPIO_DRV_OFFSET(pin);
+	struct sunxi_gpio *pio =
+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+
+	drv = readl(&pio->drv[0] + index);
+	drv &= ~(0x3 << offset);
+	drv |= val << offset;
+
+	writel(drv, &pio->drv[0] + index);
+
+	return 0;
+}
+
+int sunxi_gpio_set_pull(u32 pin, u32 val)
+{
+	u32 pull;
+	u32 bank = GPIO_BANK(pin);
+	u32 index = GPIO_PULL_INDEX(pin);
+	u32 offset = GPIO_PULL_OFFSET(pin);
+	struct sunxi_gpio *pio =
+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
+
+	pull = readl(&pio->pull[0] + index);
+	pull &= ~(0x3 << offset);
+	pull |= val << offset;
+
+	writel(pull, &pio->pull[0] + index);
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
new file mode 100644
index 0000000..79b4f21
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SUNXI_GPIO_H
+#define _SUNXI_GPIO_H
+
+#include <linux/types.h>
+
+/*
+ * sunxi has 9 banks of gpio, they are:
+ * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
+ * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
+ * PG0 - PG9  | PH0 - PH27 | PI0 - PI12
+ */
+
+#define SUNXI_GPIO_A	0
+#define SUNXI_GPIO_B	1
+#define SUNXI_GPIO_C	2
+#define SUNXI_GPIO_D	3
+#define SUNXI_GPIO_E	4
+#define SUNXI_GPIO_F	5
+#define SUNXI_GPIO_G	6
+#define SUNXI_GPIO_H	7
+#define SUNXI_GPIO_I	8
+
+struct sunxi_gpio {
+	u32 cfg[4];
+	u32 dat;
+	u32 drv[2];
+	u32 pull[2];
+};
+
+/* gpio interrupt control */
+struct sunxi_gpio_int {
+	u32 cfg[3];
+	u32 ctl;
+	u32 sta;
+	u32 deb;		/* interrupt debounce */
+};
+
+struct sunxi_gpio_reg {
+	struct sunxi_gpio gpio_bank[9];
+	u8 res[0xbc];
+	struct sunxi_gpio_int gpio_int;
+};
+
+#define GPIO_BANK(pin)		((pin) >> 5)
+#define GPIO_NUM(pin)		((pin) & 0x1f)
+
+#define GPIO_CFG_INDEX(pin)	(((pin) & 0x1f) >> 3)
+#define GPIO_CFG_OFFSET(pin)	((((pin) & 0x1f) & 0x7) << 2)
+
+#define GPIO_DRV_INDEX(pin)   (((pin) & 0x1f) >> 4)
+#define GPIO_DRV_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
+
+#define GPIO_PULL_INDEX(pin)	(((pin) & 0x1f) >> 4)
+#define GPIO_PULL_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
+
+/* GPIO bank sizes */
+#define SUNXI_GPIO_A_NR		32
+#define SUNXI_GPIO_B_NR		32
+#define SUNXI_GPIO_C_NR		32
+#define SUNXI_GPIO_D_NR		32
+#define SUNXI_GPIO_E_NR		32
+#define SUNXI_GPIO_F_NR		32
+#define SUNXI_GPIO_G_NR		32
+#define SUNXI_GPIO_H_NR		32
+#define SUNXI_GPIO_I_NR		32
+
+#define SUNXI_GPIO_NEXT(__gpio) \
+	((__gpio##_START) + (__gpio##_NR) + 0)
+
+enum sunxi_gpio_number {
+	SUNXI_GPIO_A_START = 0,
+	SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
+	SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
+	SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
+	SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
+	SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
+	SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
+	SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
+	SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
+};
+
+/* SUNXI GPIO number definitions */
+#define SUNXI_GPA(_nr)	(SUNXI_GPIO_A_START + (_nr))
+#define SUNXI_GPB(_nr)	(SUNXI_GPIO_B_START + (_nr))
+#define SUNXI_GPC(_nr)	(SUNXI_GPIO_C_START + (_nr))
+#define SUNXI_GPD(_nr)	(SUNXI_GPIO_D_START + (_nr))
+#define SUNXI_GPE(_nr)	(SUNXI_GPIO_E_START + (_nr))
+#define SUNXI_GPF(_nr)	(SUNXI_GPIO_F_START + (_nr))
+#define SUNXI_GPG(_nr)	(SUNXI_GPIO_G_START + (_nr))
+#define SUNXI_GPH(_nr)	(SUNXI_GPIO_H_START + (_nr))
+#define SUNXI_GPI(_nr)	(SUNXI_GPIO_I_START + (_nr))
+
+/* GPIO pin function config */
+#define SUNXI_GPIO_INPUT	0
+#define SUNXI_GPIO_OUTPUT	1
+
+#define SUNXI_GPA0_ERXD3	2
+#define SUNXI_GPA0_SPI1_CS0	3
+#define SUNXI_GPA0_UART2_RTS	4
+
+#define SUNXI_GPA1_ERXD2	2
+#define SUNXI_GPA1_SPI1_CLK	3
+#define SUNXI_GPA1_UART2_CTS	4
+
+#define SUNXI_GPA2_ERXD1	2
+#define SUNXI_GPA2_SPI1_MOSI	3
+#define SUNXI_GPA2_UART2_TX	4
+
+#define SUNXI_GPA10_UART1_TX	4
+#define SUNXI_GPA11_UART1_RX	4
+
+#define SUN4I_GPB22_UART0_TX	2
+#define SUN4I_GPB23_UART0_RX	2
+
+#define SUN5I_GPB19_UART0_TX	2
+#define SUN5I_GPB20_UART0_RX	2
+
+#define SUN5I_GPG3_UART0_TX	4
+#define SUN5I_GPG4_UART0_RX	4
+
+#define SUNXI_GPC2_NCLE		2
+#define SUNXI_GPC2_SPI0_CLK	3
+
+#define SUNXI_GPC6_NRB0		2
+#define SUNXI_GPC6_SDC2_CMD	3
+
+#define SUNXI_GPC7_NRB1		2
+#define SUNXI_GPC7_SDC2_CLK	3
+
+#define SUNXI_GPC8_NDQ0		2
+#define SUNXI_GPC8_SDC2_D0	3
+
+#define SUNXI_GPC9_NDQ1		2
+#define SUNXI_GPC9_SDC2_D1	3
+
+#define SUNXI_GPC10_NDQ2	2
+#define SUNXI_GPC10_SDC2_D2	3
+
+#define SUNXI_GPC11_NDQ3	2
+#define SUNXI_GPC11_SDC2_D3	3
+
+#define SUNXI_GPF2_SDC0_CLK	2
+#define SUNXI_GPF2_UART0_TX	4
+
+#define SUNXI_GPF4_SDC0_D3	2
+#define SUNXI_GPF4_UART0_RX	4
+
+int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgpin(u32 pin);
+int sunxi_gpio_set_drv(u32 pin, u32 val);
+int sunxi_gpio_set_pull(u32 pin, u32 val);
+int name_to_gpio(const char *name);
+#define name_to_gpio	name_to_gpio
+
+#endif /* _SUNXI_GPIO_H */
-- 
1.8.5.3

[U-Boot] [PATCH v1 2/9] sunxi: initial sun7i pinmux and gpio support

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:44AM +0000, Ian Campbell wrote:

> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> ldscripts" vs v2014.01.
> 
> This has been stripped back for mainlining and supports only sun7i. These
> changes are not useful by themselves but are split out to make the patch sizes
> more manageable.
> 
> As well as the following signed-off-by the sunxi branch shows commits to these
> files authored by the following:
>   Carl van Schaik
>   Henrik Nordstrom
>   Stefan Roese
>   Tom Cubie
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>

Aside from the global comments:

Reviewed-by: Tom Rini <trini@ti.com>

-- 
Tom
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[U-Boot] [PATCH v1 3/9] sunxi: initial sun7i dram setup support

[Ian Campbell]

Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
ldscripts" vs v2014.01.

This has been stripped back for mainlining and supports only sun7i. These
changes are not useful by themselves but are split out to make the patch sizes
more manageable.

As well as the following signed-off-by the sunxi branch shows commits to these
files authored by the following:
  Alejandro Mery
  Carl van Schaik
  Tom Cubie

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/sunxi/Makefile      |   1 +
 arch/arm/cpu/armv7/sunxi/dram.c        | 530 +++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/dram.h | 191 ++++++++++++
 3 files changed, 722 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/dram.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index b4298c0..41d843f 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -25,5 +25,6 @@
 #
 
 obj-y	+= timer.o
+obj-y	+= dram.o
 obj-y	+= clock.o
 obj-y	+= pinmux.o
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
new file mode 100644
index 0000000..81b1f50
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram.c
@@ -0,0 +1,530 @@
+/*
+ * sunxi DRAM controller initialization
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
+ * and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/sys_proto.h>
+
+#define CPU_CFG_CHIP_VER(n) ((n) << 6)
+#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
+#define CPU_CFG_CHIP_REV_A 0x0
+#define CPU_CFG_CHIP_REV_C1 0x1
+#define CPU_CFG_CHIP_REV_C2 0x2
+#define CPU_CFG_CHIP_REV_B 0x3
+
+static void mctl_ddr3_reset(void)
+{
+	struct sunxi_dram_reg *dram =
+			(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+	{
+		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+		udelay(2);
+		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+	}
+}
+
+static void mctl_set_drive(void)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
+			DRAM_MCR_MODE_EN(0x3) |
+			0xffc);
+}
+
+static void mctl_itm_disable(void)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+	clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
+}
+
+static void mctl_itm_enable(void)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+	clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
+}
+
+static void mctl_enable_dll0(u32 phase)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+	clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
+			((phase >> 16) & 0x3f) << 6);
+	clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
+	udelay(2);
+
+	clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
+	udelay(22);
+
+	clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
+	udelay(22);
+}
+
+/*
+ * Note: This differs from pm/standby in that it checks the bus width
+ */
+static void mctl_enable_dllx(u32 phase)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+	u32 i, n, bus_width;
+
+	bus_width = readl(&dram->dcr);
+
+	if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) ==
+	    DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
+		n = DRAM_DCR_NR_DLLCR_32BIT;
+	else
+		n = DRAM_DCR_NR_DLLCR_16BIT;
+
+	for (i = 1; i < n; i++) {
+		clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
+				(phase & 0xf) << 14);
+		clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
+				DRAM_DLLCR_DISABLE);
+		phase >>= 4;
+	}
+	udelay(2);
+
+	for (i = 1; i < n; i++)
+		clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
+			     DRAM_DLLCR_DISABLE);
+	udelay(22);
+
+	for (i = 1; i < n; i++)
+		clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
+				DRAM_DLLCR_NRESET);
+	udelay(22);
+}
+
+static u32 hpcr_value[32] = {
+	0x0301, 0x0301, 0x0301, 0x0301,
+	0x0301, 0x0301, 0x0301, 0x0301,
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	0x1031, 0x1031, 0x0735, 0x1035,
+	0x1035, 0x0731, 0x1031, 0x0735,
+	0x1035, 0x1031, 0x0731, 0x1035,
+	0x0001, 0x1031, 0, 0x1031
+	/* last row differs from boot0 source table
+	 * 0x1031, 0x0301, 0x0301, 0x0731
+	 * but boot0 code skips #28 and #30, and sets #29 and #31 to the
+	 * value from #28 entry (0x1031)
+         */
+};
+
+static void mctl_configure_hostport(void)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+	u32 i;
+
+	for (i = 0; i < 32; i++)
+		writel(hpcr_value[i], &dram->hpcr[i]);
+}
+
+static void mctl_setup_dram_clock(u32 clk)
+{
+	u32 reg_val;
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* setup DRAM PLL */
+	reg_val = readl(&ccm->pll5_cfg);
+	reg_val &= ~CCM_PLL5_CTRL_M_MASK;		/* set M to 0 (x1) */
+	reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
+	reg_val &= ~CCM_PLL5_CTRL_K_MASK;		/* set K to 0 (x1) */
+	reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
+	reg_val &= ~CCM_PLL5_CTRL_N_MASK;		/* set N to 0 (x0) */
+	reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
+	reg_val &= ~CCM_PLL5_CTRL_P_MASK;		/* set P to 0 (x1) */
+	reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
+	reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN;		/* PLL VCO Gain off */
+	reg_val |= CCM_PLL5_CTRL_EN;			/* PLL On */
+	writel(reg_val, &ccm->pll5_cfg);
+	udelay(5500);
+
+	setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
+
+	/* reset GPS */
+	clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
+	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
+	udelay(1);
+	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
+
+	/* setup MBUS clock */
+	reg_val = CCM_MBUS_CTRL_GATE |
+		  CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
+		  CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
+		  CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+	writel(reg_val, &ccm->mbus_clk_cfg);
+
+	/*
+	 * open DRAMC AHB & DLL register clock
+	 * close it first
+	 */
+	clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+	udelay(22);
+
+	/* then open it */
+	setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+	udelay(22);
+}
+
+static int dramc_scan_readpipe(void)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+	u32 reg_val;
+
+	/* data training trigger */
+	clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
+	setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
+
+	/* check whether data training process has completed */
+	while (readl(&dram->ccr) & DRAM_CCR_DATA_TRAINING);
+
+	/* check data training result */
+	reg_val = readl(&dram->csr);
+	if (reg_val & DRAM_CSR_FAILED)
+		return -1;
+
+	return 0;
+}
+
+static int dramc_scan_dll_para(void)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+	const u32 dqs_dly[7] = {0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc};
+	const u32 clk_dly[15] = {0x07, 0x06, 0x05, 0x04, 0x03,
+				 0x02, 0x01, 0x00, 0x08, 0x10,
+				 0x18, 0x20, 0x28, 0x30, 0x38};
+	u32 clk_dqs_count[15];
+	u32 dqs_i, clk_i, cr_i;
+	u32 max_val, min_val;
+	u32 dqs_index, clk_index;
+
+	/* Find DQS_DLY Pass Count for every CLK_DLY */
+	for (clk_i = 0; clk_i < 15; clk_i++) {
+		clk_dqs_count[clk_i] = 0;
+		clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
+				(clk_dly[clk_i] & 0x3f) << 6);
+		for (dqs_i = 0; dqs_i < 7; dqs_i++) {
+			for (cr_i = 1; cr_i < 5; cr_i++) {
+				clrsetbits_le32(&dram->dllcr[cr_i],
+						0x4f << 14,
+						(dqs_dly[dqs_i] & 0x4f) << 14);
+			}
+			udelay(2);
+			if (dramc_scan_readpipe() == 0)
+				clk_dqs_count[clk_i]++;
+		}
+	}
+	/* Test DQS_DLY Pass Count for every CLK_DLY from up to down */
+	for (dqs_i = 15; dqs_i > 0; dqs_i--) {
+		max_val = 15;
+		min_val = 15;
+		for (clk_i = 0; clk_i < 15; clk_i++) {
+			if (clk_dqs_count[clk_i] == dqs_i) {
+				max_val = clk_i;
+				if (min_val == 15)
+					min_val = clk_i;
+			}
+		}
+		if (max_val < 15)
+			break;
+	}
+
+	/* Check if Find a CLK_DLY failed */
+	if (!dqs_i)
+		goto fail;
+
+	/* Find the middle index of CLK_DLY */
+	clk_index = (max_val + min_val) >> 1;
+	if ((max_val == (15 - 1)) && (min_val > 0))
+		/* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle
+		 * value can be more close to the max_val
+		 */
+		clk_index = (15 + clk_index) >> 1;
+	else if ((max_val < (15 - 1)) && (min_val == 0))
+		/* if CLK_DLY[0] is very good, then the middle value can be more
+		 * close to the min_val
+		 */
+		clk_index >>= 1;
+	if (clk_dqs_count[clk_index] < dqs_i)
+		clk_index = min_val;
+
+	/* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan
+	 * read pipe again
+	 */
+	clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
+			(clk_dly[clk_index] & 0x3f) << 6);
+	max_val = 7;
+	min_val = 7;
+	for (dqs_i = 0; dqs_i < 7; dqs_i++) {
+		clk_dqs_count[dqs_i] = 0;
+		for (cr_i = 1; cr_i < 5; cr_i++) {
+			clrsetbits_le32(&dram->dllcr[cr_i],
+					0x4f << 14,
+					(dqs_dly[dqs_i] & 0x4f) << 14);
+		}
+		udelay(2);
+		if (dramc_scan_readpipe() == 0) {
+			clk_dqs_count[dqs_i] = 1;
+			max_val = dqs_i;
+			if (min_val == 7)
+				min_val = dqs_i;
+		}
+	}
+
+	if (max_val < 7) {
+		dqs_index = (max_val + min_val) >> 1;
+		if ((max_val == (7-1)) && (min_val > 0))
+			dqs_index = (7 + dqs_index) >> 1;
+		else if ((max_val < (7-1)) && (min_val == 0))
+			dqs_index >>= 1;
+		if (!clk_dqs_count[dqs_index])
+			dqs_index = min_val;
+		for (cr_i = 1; cr_i < 5; cr_i++) {
+			clrsetbits_le32(&dram->dllcr[cr_i],
+					0x4f << 14,
+					(dqs_dly[dqs_index] & 0x4f) << 14);
+		}
+		udelay(2);
+		return dramc_scan_readpipe();
+	}
+
+fail:
+	clrbits_le32(&dram->dllcr[0], 0x3f << 6);
+	for (cr_i = 1; cr_i < 5; cr_i++)
+		clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14);
+	udelay(2);
+
+	return dramc_scan_readpipe();
+}
+
+static void dramc_clock_output_en(u32 on)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+	if (on)
+		setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
+	else
+		clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
+}
+
+
+static void dramc_set_autorefresh_cycle(u32 clk)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+	u32 reg_val;
+	u32 tmp_val;
+	reg_val = 0x83;
+
+	tmp_val = (7987 * clk) >> 10;
+	tmp_val = tmp_val * 9 - 200;
+	reg_val |= tmp_val << 8;
+	reg_val |= 0x8 << 24;
+	writel(reg_val, &dram->drr);
+}
+
+unsigned long dramc_init(struct dram_para *para)
+{
+	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+	u32 reg_val;
+	int ret_val;
+
+	/* check input dram parameter structure */
+	if (!para)
+		return 0;
+
+	/* setup DRAM relative clock */
+	mctl_setup_dram_clock(para->clock);
+
+	/* reset external DRAM */
+	mctl_ddr3_reset();
+	mctl_set_drive();
+
+	/* dram clock off */
+	dramc_clock_output_en(0);
+
+	mctl_itm_disable();
+	mctl_enable_dll0(para->tpr3);
+
+	/* configure external DRAM */
+	reg_val = 0x0;
+	if (para->type == DRAM_MEMORY_TYPE_DDR3)
+		reg_val |= DRAM_DCR_TYPE_DDR3;
+	reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
+
+	if (para->density == 256)
+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M);
+	else if (para->density == 512)
+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_512M);
+	else if (para->density == 1024)
+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_1024M);
+	else if (para->density == 2048)
+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_2048M);
+	else if (para->density == 4096)
+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_4096M);
+	else if (para->density == 8192)
+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_8192M);
+	else
+		reg_val |= DRAM_DCR_CHIP_DENSITY(DRAM_DCR_CHIP_DENSITY_256M);
+
+	reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
+	reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
+	reg_val |= DRAM_DCR_CMD_RANK_ALL;
+	reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
+	writel(reg_val, &dram->dcr);
+
+	setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1));
+	if (para->tpr4 & 0x2)
+		clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1));
+	dramc_clock_output_en(1);
+
+	/* set odt impendance divide ratio */
+	reg_val = ((para->zq) >> 8) & 0xfffff;
+	reg_val |= ((para->zq) & 0xff) << 20;
+	reg_val |= (para->zq) & 0xf0000000;
+	writel(reg_val, &dram->zqcr0);
+
+	/* Set CKE Delay to about 1ms */
+	setbits_le32(&dram->idcr, 0x1ffff);
+
+	if ((readl(&dram->ppwrsctl) & 0x1) != 0x1)
+		mctl_ddr3_reset();
+	else
+		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+
+	udelay(1);
+
+	while (readl(&dram->ccr) & DRAM_CCR_INIT);
+
+	mctl_enable_dllx(para->tpr3);
+
+	/* set refresh period */
+	dramc_set_autorefresh_cycle(para->clock);
+
+	/* set timing parameters */
+	writel(para->tpr0, &dram->tpr0);
+	writel(para->tpr1, &dram->tpr1);
+	writel(para->tpr2, &dram->tpr2);
+
+	if (para->type == DRAM_MEMORY_TYPE_DDR3) {
+		reg_val = DRAM_MR_BURST_LENGTH(0x0);
+		reg_val |= DRAM_MR_POWER_DOWN;
+		reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
+		reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
+	} else if (para->type == DRAM_MEMORY_TYPE_DDR2) {
+		reg_val = DRAM_MR_BURST_LENGTH(0x2);
+		reg_val |= DRAM_MR_CAS_LAT(para->cas);
+		reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
+	}
+	writel(reg_val, &dram->mr);
+
+	writel(para->emr1, &dram->emr);
+	writel(para->emr2, &dram->emr2);
+	writel(para->emr3, &dram->emr3);
+
+	/* set DQS window mode */
+	clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
+
+	/* Command rate timing mode 2T & 1T */
+	if (para->tpr4 & 0x1)
+		setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
+	/* reset external DRAM */
+	setbits_le32(&dram->ccr, DRAM_CCR_INIT);
+	while (readl(&dram->ccr) & DRAM_CCR_INIT);
+
+	/* setup zq calibration manual */
+	reg_val = readl(&dram->ppwrsctl);
+	if ((reg_val & 0x1) == 1) {
+		/* super_standby_flag = 1 */
+
+		reg_val = readl(0x01c20c00 + 0x120); /* rtc */
+		reg_val &= 0x000fffff;
+		reg_val |= 0x17b00000;
+		writel(reg_val, &dram->zqcr0);
+
+		/* exit self-refresh state */
+		clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
+		/* check whether command has been executed */
+		while (readl(&dram->dcr) & (0x1 << 31));
+
+		udelay(2);
+
+		/* dram pad hold off */
+		setbits_le32(&dram->ppwrsctl, 0x16510000);
+
+		while (readl(&dram->ppwrsctl) & 0x1);
+
+		/* exit self-refresh state */
+		clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
+
+		/* check whether command has been executed */
+		while (readl(&dram->dcr) & (0x1 << 31));
+		udelay(2);;
+
+		/* issue a refresh command */
+		clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x13 << 27);
+		while (readl(&dram->dcr) & (0x1 << 31));
+
+		udelay(2);
+	}
+
+	/* scan read pipe value */
+	mctl_itm_enable();
+	if (para->tpr3 & (0x1 << 31)) {
+		ret_val = dramc_scan_dll_para();
+		if (ret_val == 0)
+			para->tpr3 =
+				(((readl(&dram->dllcr[0]) >> 6) & 0x3f) << 16) |
+				(((readl(&dram->dllcr[1]) >> 14) & 0xf) << 0) |
+				(((readl(&dram->dllcr[2]) >> 14) & 0xf) << 4) |
+				(((readl(&dram->dllcr[3]) >> 14) & 0xf) << 8) |
+				(((readl(&dram->dllcr[4]) >> 14) & 0xf) << 12
+				);
+	} else {
+		ret_val = dramc_scan_readpipe();
+	}
+
+	if (ret_val < 0)
+		return 0;
+
+	/* configure all host port */
+	mctl_configure_hostport();
+
+	return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
+}
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
new file mode 100644
index 0000000..d2d18f0
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -0,0 +1,191 @@
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Sunxi platform dram register definition.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SUNXI_DRAM_H
+#define _SUNXI_DRAM_H
+
+#include <linux/types.h>
+
+struct sunxi_dram_reg {
+	u32 ccr;		/* 0x00 controller configuration register */
+	u32 dcr;		/* 0x04 dram configuration register */
+	u32 iocr;		/* 0x08 i/o configuration register */
+	u32 csr;		/* 0x0c controller status register */
+	u32 drr;		/* 0x10 dram refresh register */
+	u32 tpr0;		/* 0x14 dram timing parameters register 0 */
+	u32 tpr1;		/* 0x18 dram timing parameters register 1 */
+	u32 tpr2;		/* 0x1c dram timing parameters register 2 */
+	u32 gdllcr;		/* 0x20 global dll control register */
+	u8 res0[0x28];
+	u32 rslr0;		/* 0x4c rank system latency register */
+	u32 rslr1;		/* 0x50 rank system latency register */
+	u8 res1[0x8];
+	u32 rdgr0;		/* 0x5c rank dqs gating register */
+	u32 rdgr1;		/* 0x60 rank dqs gating register */
+	u8 res2[0x34];
+	u32 odtcr;		/* 0x98 odt configuration register */
+	u32 dtr0;		/* 0x9c data training register 0 */
+	u32 dtr1;		/* 0xa0 data training register 1 */
+	u32 dtar;		/* 0xa4 data training address register */
+	u32 zqcr0;		/* 0xa8 zq control register 0 */
+	u32 zqcr1;		/* 0xac zq control register 1 */
+	u32 zqsr;		/* 0xb0 zq status register */
+	u32 idcr;		/* 0xb4 initializaton delay configure reg */
+	u8 res3[0x138];
+	u32 mr;			/* 0x1f0 mode register */
+	u32 emr;		/* 0x1f4 extended mode register */
+	u32 emr2;		/* 0x1f8 extended mode register */
+	u32 emr3;		/* 0x1fc extended mode register */
+	u32 dllctr;		/* 0x200 dll control register */
+	u32 dllcr[5];		/* 0x204 dll control register 0(byte 0) */
+	/* 0x208 dll control register 1(byte 1) */
+	/* 0x20c dll control register 2(byte 2) */
+	/* 0x210 dll control register 3(byte 3) */
+	/* 0x214 dll control register 4(byte 4) */
+	u32 dqtr0;		/* 0x218 dq timing register */
+	u32 dqtr1;		/* 0x21c dq timing register */
+	u32 dqtr2;		/* 0x220 dq timing register */
+	u32 dqtr3;		/* 0x224 dq timing register */
+	u32 dqstr;		/* 0x228 dqs timing register */
+	u32 dqsbtr;		/* 0x22c dqsb timing register */
+	u32 mcr;		/* 0x230 mode configure register */
+	u8 res[0x8];
+	u32 ppwrsctl;		/* 0x23c pad power save control */
+	u32 apr;		/* 0x240 arbiter period register */
+	u32 pldtr;		/* 0x244 priority level data threshold reg */
+	u8 res5[0x8];
+	u32 hpcr[32];		/* 0x250 host port configure register */
+	u8 res6[0x10];
+	u32 csel;		/* 0x2e0 controller select register */
+};
+
+struct dram_para {
+	u32 clock;
+	u32 type;
+	u32 rank_num;
+	u32 density;
+	u32 io_width;
+	u32 bus_width;
+	u32 cas;
+	u32 zq;
+	u32 odt_en;
+	u32 size;
+	u32 tpr0;
+	u32 tpr1;
+	u32 tpr2;
+	u32 tpr3;
+	u32 tpr4;
+	u32 tpr5;
+	u32 emr1;
+	u32 emr2;
+	u32 emr3;
+};
+
+#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
+#define DRAM_CCR_DQS_GATE (0x1 << 14)
+#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
+#define DRAM_CCR_ITM_OFF (0x1 << 28)
+#define DRAM_CCR_DATA_TRAINING (0x1 << 30)
+#define DRAM_CCR_INIT (0x1 << 31)
+
+#define DRAM_MEMORY_TYPE_DDR1 1
+#define DRAM_MEMORY_TYPE_DDR2 2
+#define DRAM_MEMORY_TYPE_DDR3 3
+#define DRAM_MEMORY_TYPE_LPDDR2 4
+#define DRAM_MEMORY_TYPE_LPDDR 5
+#define DRAM_DCR_TYPE (0x1 << 0)
+#define DRAM_DCR_TYPE_DDR2 0x0
+#define DRAM_DCR_TYPE_DDR3 0x1
+#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
+#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
+#define DRAM_DCR_IO_WIDTH_8BIT 0x0
+#define DRAM_DCR_IO_WIDTH_16BIT 0x1
+#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
+#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
+#define DRAM_DCR_CHIP_DENSITY_256M 0x0
+#define DRAM_DCR_CHIP_DENSITY_512M 0x1
+#define DRAM_DCR_CHIP_DENSITY_1024M 0x2
+#define DRAM_DCR_CHIP_DENSITY_2048M 0x3
+#define DRAM_DCR_CHIP_DENSITY_4096M 0x4
+#define DRAM_DCR_CHIP_DENSITY_8192M 0x5
+#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
+#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
+#define DRAM_DCR_BUS_WIDTH_32BIT 0x3
+#define DRAM_DCR_BUS_WIDTH_16BIT 0x1
+#define DRAM_DCR_BUS_WIDTH_8BIT 0x0
+#define DRAM_DCR_NR_DLLCR_32BIT 5
+#define DRAM_DCR_NR_DLLCR_16BIT 3
+#define DRAM_DCR_NR_DLLCR_8BIT 2
+#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
+#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
+#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
+#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
+#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
+#define DRAM_DCR_MODE_SEQ 0x0
+#define DRAM_DCR_MODE_INTERLEAVE 0x1
+
+#define DRAM_CSR_FAILED (0x1 << 20)
+
+#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
+#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
+#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
+#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
+#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
+#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
+#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
+#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
+#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
+#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
+#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
+#define DRAM_MCR_RESET (0x1 << 12)
+#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
+#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
+#define DRAM_MCR_DCLK_OUT (0x1 << 16)
+
+#define DRAM_DLLCR_NRESET (0x1 << 30)
+#define DRAM_DLLCR_DISABLE (0x1 << 31)
+
+#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
+#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
+
+#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0)
+#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
+
+#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
+#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
+#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
+#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
+#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
+#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
+#define DRAM_MR_POWER_DOWN (0x1 << 12)
+
+#define DRAM_CSEL_MAGIC 0x16237495
+
+unsigned long sunxi_dram_init(void);
+unsigned long dramc_init(struct dram_para *para);
+
+#endif /* _SUNXI_DRAM_H */
-- 
1.8.5.3

[U-Boot] [PATCH v1 3/9] sunxi: initial sun7i dram setup support

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:45AM +0000, Ian Campbell wrote:

[snip]
> +static void mctl_ddr3_reset(void)
> +{
> +	struct sunxi_dram_reg *dram =
> +			(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
> +
> +	{
> +		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
> +		udelay(2);
> +		setbits_le32(&dram->mcr, DRAM_MCR_RESET);
> +	}

That seems like an odd construction, why the extra braces?

And as for the rest of the code, lots of magic numbers to #define
what/why (why udelay(2) and 22?)

-- 
Tom
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[U-Boot] [linux-sunxi] Re: [PATCH v1 3/9] sunxi: initial sun7i dram setup support

[Henrik Nordström]

fre 2014-03-14 klockan 10:17 -0400 skrev Tom Rini:

> And as for the rest of the code, lots of magic numbers to #define
> what/why (why udelay(2) and 22?)

Unfortunately the only documentation we have on the sun7i DRAM
controller is Allwinner boot0 + boot1 code, and that code uses.. magic
numbers & shifts with no explanations.

We have guessed some small bits, but a lot is completely unknown.

Regards
Henriki

[U-Boot] [linux-sunxi] Re: [PATCH v1 3/9] sunxi: initial sun7i dram setup support

[Luke Kenneth Casson Leighton]

On Fri, Mar 14, 2014 at 4:28 PM, Henrik Nordstr?m
<henrik@henriknordstrom.net> wrote:
> fre 2014-03-14 klockan 10:17 -0400 skrev Tom Rini:
>
>> And as for the rest of the code, lots of magic numbers to #define
>> what/why (why udelay(2) and 22?)
>
> Unfortunately the only documentation we have on the sun7i DRAM
> controller is Allwinner boot0 + boot1 code, and that code uses.. magic
> numbers & shifts with no explanations.

 a terse comment at the top to that effect would likely be worthwhile.

 l.

[U-Boot] [PATCH v1 3/9] sunxi: initial sun7i dram setup support

[Stefan]

> Unfortunately the only documentation we have on the sun7i DRAM
> controller is Allwinner boot0 + boot1 code, and that code uses.. magic
> numbers & shifts with no explanations.

To avoid having to explain this over-and-over again, the code could
include some comment(s) pointing out that these are unexplained magic
constants from Allwinner's code.


        Stefan

[U-Boot] [linux-sunxi] Re: [PATCH v1 3/9] sunxi: initial sun7i dram setup support

[Ian Campbell]

On Mon, 2014-03-17 at 09:16 -0400, Stefan wrote:
> > Unfortunately the only documentation we have on the sun7i DRAM
> > controller is Allwinner boot0 + boot1 code, and that code uses.. magic
> > numbers & shifts with no explanations.
> 
> To avoid having to explain this over-and-over again, the code could
> include some comment(s) pointing out that these are unexplained magic
> constants from Allwinner's code.

This is what I plan to do.

Ian.

[U-Boot] [PATCH v1 3/9] sunxi: initial sun7i dram setup support

[Alex G.]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 03/14/2014 09:17 AM, Tom Rini wrote:
> On Fri, Mar 14, 2014 at 10:33:45AM +0000, Ian Campbell wrote:
> 
> [snip]
>> +static void mctl_ddr3_reset(void) +{ +	struct sunxi_dram_reg 
>> *dram = +			(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + +	{ + 
>> clrbits_le32(&dram->mcr, DRAM_MCR_RESET); +		udelay(2); + 
>> setbits_le32(&dram->mcr, DRAM_MCR_RESET); +	}
> 
> That seems like an odd construction, why the extra braces?
> 
This originally had a conditional depending on the SoC family. (Yeah,
they need to reset the ram differently). It seems it wasn't removed
properly.

> And as for the rest of the code, lots of magic numbers to #define 
> what/why (why udelay(2) and 22?)
> 
Before going into more detail, remember this is ram initialization
code. That's always going to be a pain :(.
There's nothing magic here. It's just a fact of life. Every step is
going to need a different delay. No need to bloat the headers by
#defining each. It also makes raminit code more unreadable.

We got these numbers from allwinner code dumps. We used to have these
as sdelay() numbers, which usually meant units of 2 clock cycles. So
we had to convert them to udelay() to at least make the delays
independent of CPU clock. The old sdelay() numbers made no sense either.

Alex
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[U-Boot] [PATCH v1 3/9] sunxi: initial sun7i dram setup support

[Tom Rini]

On Fri, Mar 14, 2014 at 12:23:50PM -0500, Alex G. wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> On 03/14/2014 09:17 AM, Tom Rini wrote:
> > On Fri, Mar 14, 2014 at 10:33:45AM +0000, Ian Campbell wrote:
> > 
> > [snip]
> >> +static void mctl_ddr3_reset(void) +{ +	struct sunxi_dram_reg 
> >> *dram = +			(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + +	{ + 
> >> clrbits_le32(&dram->mcr, DRAM_MCR_RESET); +		udelay(2); + 
> >> setbits_le32(&dram->mcr, DRAM_MCR_RESET); +	}
> > 
> > That seems like an odd construction, why the extra braces?
> > 
> This originally had a conditional depending on the SoC family. (Yeah,
> they need to reset the ram differently). It seems it wasn't removed
> properly.
> 
> > And as for the rest of the code, lots of magic numbers to #define 
> > what/why (why udelay(2) and 22?)
> > 
> Before going into more detail, remember this is ram initialization
> code. That's always going to be a pain :(.
> There's nothing magic here. It's just a fact of life. Every step is
> going to need a different delay. No need to bloat the headers by
> #defining each. It also makes raminit code more unreadable.
> 
> We got these numbers from allwinner code dumps. We used to have these
> as sdelay() numbers, which usually meant units of 2 clock cycles. So
> we had to convert them to udelay() to at least make the delays
> independent of CPU clock. The old sdelay() numbers made no sense either.

Yeah, I can accept a certain amount of black magic here.  We need to
make sure things are commented as much as it can be.

-- 
Tom
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[U-Boot] [PATCH v1 4/9] sunxi: initial generic sun7i cpu, board and start of day support

[Ian Campbell]

Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
ldscripts" vs v2014.01.

This has been stripped back for mainlining and supports only sun7i. These
changes are not useful by themselves but are split out to make the patch sizes
more manageable.

As well as the following signed-off-by the sunxi branch shows commits to these
files authored by the following:
  Almo Nito
  Carl van Schaik
  FUKAUMI Naoki
  hehopmajieh
  j
  Sergey Lapin
  Tom Cubie

Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Patrick Wood <patrickhwood@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/sunxi/Makefile     |  11 +++
 arch/arm/cpu/armv7/sunxi/board.c      | 104 +++++++++++++++++++++++++
 arch/arm/cpu/armv7/sunxi/cpu_info.c   |  35 +++++++++
 arch/arm/cpu/armv7/sunxi/start.c      |   1 +
 arch/arm/include/asm/arch-sunxi/cpu.h | 138 ++++++++++++++++++++++++++++++++++
 board/sunxi/Makefile                  |  28 +++++++
 board/sunxi/board.c                   |  91 ++++++++++++++++++++++
 7 files changed, 408 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/board.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/cpu_info.c
 create mode 100644 arch/arm/cpu/armv7/sunxi/start.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpu.h
 create mode 100644 board/sunxi/Makefile
 create mode 100644 board/sunxi/board.c

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 41d843f..3e8a36c 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -26,5 +26,16 @@
 
 obj-y	+= timer.o
 obj-y	+= dram.o
+obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= pinmux.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y	+= cpu_info.o
+endif
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_FEL
+obj-y	+= start.o
+endif
+endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
new file mode 100644
index 0000000..98cad43
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Some init for sunxi platform.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <serial.h>
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#endif
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/timer.h>
+
+#ifdef CONFIG_SPL_BUILD
+/* Pointer to the global data structure for SPL */
+DECLARE_GLOBAL_DATA_PTR;
+
+/* The sunxi internal brom will try to loader external bootloader
+ * from mmc0, nannd flash, mmc2.
+ * Unfortunately we can't check how SPL was loaded so assume
+ * it's always the first SD/MMC controller
+ */
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}
+
+/* No confirmation data available in SPL yet. Hardcode bootmode */
+u32 spl_boot_mode(void)
+{
+	return MMCSD_MODE_RAW;
+}
+#endif
+
+int gpio_init(void)
+{
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+/* do some early init */
+void s_init(void)
+{
+#if !defined CONFIG_SPL_BUILD
+	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
+	asm volatile(
+		"mrc p15, 0, r0, c1, c0, 1\n"
+		"orr r0, r0, #0x40\n"
+		"mcr p15, 0, r0, c1, c0, 1\n");
+#endif
+
+	clock_init();
+	timer_init();
+	gpio_init();
+
+#ifdef CONFIG_SPL_BUILD
+	gd = &gdata;
+	preloader_console_init();
+
+	sunxi_board_init();
+#endif
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
new file mode 100644
index 0000000..14093dd
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+	puts("CPU:   Allwinner A20 (SUN7I)\n");
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/start.c b/arch/arm/cpu/armv7/sunxi/start.c
new file mode 100644
index 0000000..6b392fa
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/start.c
@@ -0,0 +1 @@
+/* Intentionally empty. Only needed to get FEL SPL link line right */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
new file mode 100644
index 0000000..61af3e0
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SUNXI_CPU_H
+#define _SUNXI_CPU_H
+
+#define SUNXI_SRAM_A1_BASE		0x00000000
+#define SUNXI_SRAM_A1_SIZE		(16 * 1024)	/* 16 kiB */
+
+#define SUNXI_SRAM_A2_BASE		0x00004000	/* 16 kiB */
+#define SUNXI_SRAM_A3_BASE		0x00008000	/* 13 kiB */
+#define SUNXI_SRAM_A4_BASE		0x0000b400	/* 3 kiB */
+#define SUNXI_SRAM_D_BASE		0x01c00000
+#define SUNXI_SRAM_B_BASE		0x01c00000	/* 64 kiB (secure) */
+
+#define SUNXI_SRAMC_BASE		0x01c00000
+#define SUNXI_DRAMC_BASE		0x01c01000
+#define SUNXI_DMA_BASE			0x01c02000
+#define SUNXI_NFC_BASE			0x01c03000
+#define SUNXI_TS_BASE			0x01c04000
+#define SUNXI_SPI0_BASE			0x01c05000
+#define SUNXI_SPI1_BASE			0x01c06000
+#define SUNXI_MS_BASE			0x01c07000
+#define SUNXI_TVD_BASE			0x01c08000
+#define SUNXI_CSI0_BASE			0x01c09000
+#define SUNXI_TVE0_BASE			0x01c0a000
+#define SUNXI_EMAC_BASE			0x01c0b000
+#define SUNXI_LCD0_BASE			0x01c0C000
+#define SUNXI_LCD1_BASE			0x01c0d000
+#define SUNXI_VE_BASE			0x01c0e000
+#define SUNXI_MMC0_BASE			0x01c0f000
+#define SUNXI_MMC1_BASE			0x01c10000
+#define SUNXI_MMC2_BASE			0x01c11000
+#define SUNXI_MMC3_BASE			0x01c12000
+#define SUNXI_USB0_BASE			0x01c13000
+#define SUNXI_USB1_BASE			0x01c14000
+#define SUNXI_SS_BASE			0x01c15000
+#define SUNXI_HDMI_BASE			0x01c16000
+#define SUNXI_SPI2_BASE			0x01c17000
+#define SUNXI_SATA_BASE			0x01c18000
+#define SUNXI_PATA_BASE			0x01c19000
+#define SUNXI_ACE_BASE			0x01c1a000
+#define SUNXI_TVE1_BASE			0x01c1b000
+#define SUNXI_USB2_BASE			0x01c1c000
+#define SUNXI_CSI1_BASE			0x01c1d000
+#define SUNXI_TZASC_BASE		0x01c1e000
+#define SUNXI_SPI3_BASE			0x01c1f000
+
+#define SUNXI_CCM_BASE			0x01c20000
+#define SUNXI_INTC_BASE			0x01c20400
+#define SUNXI_PIO_BASE			0x01c20800
+#define SUNXI_TIMER_BASE		0x01c20c00
+#define SUNXI_SPDIF_BASE		0x01c21000
+#define SUNXI_AC97_BASE			0x01c21400
+#define SUNXI_IR0_BASE			0x01c21800
+#define SUNXI_IR1_BASE			0x01c21c00
+
+#define SUNXI_IIS_BASE			0x01c22400
+#define SUNXI_LRADC_BASE		0x01c22800
+#define SUNXI_AD_DA_BASE		0x01c22c00
+#define SUNXI_KEYPAD_BASE		0x01c23000
+#define SUNXI_TZPC_BASE			0x01c23400
+#define SUNXI_SID_BASE			0x01c23800
+#define SUNXI_SJTAG_BASE		0x01c23c00
+
+#define SUNXI_TP_BASE			0x01c25000
+#define SUNXI_PMU_BASE			0x01c25400
+#define SUNXI_CPUCFG_BASE		0x01c25c00	/* sun7i only ? */
+
+#define SUNXI_UART0_BASE		0x01c28000
+#define SUNXI_UART1_BASE		0x01c28400
+#define SUNXI_UART2_BASE		0x01c28800
+#define SUNXI_UART3_BASE		0x01c28c00
+#define SUNXI_UART4_BASE		0x01c29000
+#define SUNXI_UART5_BASE		0x01c29400
+#define SUNXI_UART6_BASE		0x01c29800
+#define SUNXI_UART7_BASE		0x01c29c00
+#define SUNXI_PS2_0_BASE		0x01c2a000
+#define SUNXI_PS2_1_BASE		0x01c2a400
+
+#define SUNXI_TWI0_BASE			0x01c2ac00
+#define SUNXI_TWI1_BASE			0x01c2b000
+#define SUNXI_TWI2_BASE			0x01c2b400
+
+#define SUNXI_CAN_BASE			0x01c2bc00
+
+#define SUNXI_SCR_BASE			0x01c2c400
+
+#define SUNXI_GPS_BASE			0x01c30000
+#define SUNXI_MALI400_BASE		0x01c40000
+#define SUNXI_GMAC_BASE			0x01c50000
+
+/* module sram */
+#define SUNXI_SRAM_C_BASE		0x01d00000
+
+#define SUNXI_DE_FE0_BASE		0x01e00000
+#define SUNXI_DE_FE1_BASE		0x01e20000
+#define SUNXI_DE_BE0_BASE		0x01e60000
+#define SUNXI_DE_BE1_BASE		0x01e40000
+#define SUNXI_MP_BASE			0x01e80000
+#define SUNXI_AVG_BASE			0x01ea0000
+
+/* CoreSight Debug Module */
+#define SUNXI_CSDM_BASE			0x3f500000
+
+#define SUNXI_DDRII_DDRIII_BASE		0x40000000	/* 2 GiB */
+
+#define SUNXI_BROM_BASE			0xffff0000	/* 32 kiB */
+
+#define SUNXI_CPU_CFG			(SUNXI_TIMER_BASE + 0x13c)
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+extern void sunxi_reset(void);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _CPU_H */
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
new file mode 100644
index 0000000..b8c26ab
--- /dev/null
+++ b/board/sunxi/Makefile
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+#
+# Based on some other board Makefile
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+obj-y	+= board.o
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
new file mode 100644
index 0000000..bffef4f
--- /dev/null
+++ b/board/sunxi/board.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Some board init for the Allwinner A10-evb board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* add board specific code here */
+int board_init(void)
+{
+	int id_pfr1;
+
+	gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
+
+	asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
+	debug("id_pfr1: 0x%08x\n", id_pfr1);
+	/* Generic Timer Extension available? */
+	if ((id_pfr1 >> 16) & 0xf) {
+		debug("Setting CNTFRQ\n");
+		/* CNTFRQ == 24 MHz */
+		asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void sunxi_board_init(void)
+{
+	int power_failed = 0;
+	unsigned long ramsize;
+
+	printf("DRAM:");
+	ramsize = sunxi_dram_init();
+	if (!ramsize) {
+		printf(" ?");
+		ramsize = sunxi_dram_init();
+	}
+	if (!ramsize) {
+		printf(" ?");
+		ramsize = sunxi_dram_init();
+	}
+	printf(" %lu MiB\n", ramsize >> 20);
+	if (!ramsize)
+		hang();
+
+	/*
+	 * Only clock up the CPU to full speed if we are reasonably
+	 * assured it's being powered with suitable core voltage
+	 */
+	if (!power_failed)
+		clock_set_pll1(912000000);
+	else
+		printf("Failed to set core voltage! Can't set CPU frequency\n");
+}
+#endif
-- 
1.8.5.3

[U-Boot] [PATCH v1 4/9] sunxi: initial generic sun7i cpu, board and start of day support

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:46AM +0000, Ian Campbell wrote:

[snip]
> +/* The sunxi internal brom will try to loader external bootloader
> + * from mmc0, nannd flash, mmc2.

Typo.

> +#ifdef CONFIG_SPL_BUILD
> +void sunxi_board_init(void)
> +{
> +	int power_failed = 0;
> +	unsigned long ramsize;
> +
> +	printf("DRAM:");
> +	ramsize = sunxi_dram_init();
> +	if (!ramsize) {
> +		printf(" ?");
> +		ramsize = sunxi_dram_init();
> +	}
> +	if (!ramsize) {
> +		printf(" ?");
> +		ramsize = sunxi_dram_init();
> +	}

We have to try 3 times?  What?

> +	/*
> +	 * Only clock up the CPU to full speed if we are reasonably
> +	 * assured it's being powered with suitable core voltage
> +	 */
> +	if (!power_failed)
> +		clock_set_pll1(912000000);

Define that please.

-- 
Tom
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[U-Boot] [PATCH v1 4/9] sunxi: initial generic sun7i cpu, board and start of day support

[Alex G.]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 03/14/2014 09:17 AM, Tom Rini wrote:
> On Fri, Mar 14, 2014 at 10:33:46AM +0000, Ian Campbell wrote:
>> +#ifdef CONFIG_SPL_BUILD +void sunxi_board_init(void) +{ +	int
>> power_failed = 0; +	unsigned long ramsize; + +	printf("DRAM:"); +
>> ramsize = sunxi_dram_init(); +	if (!ramsize) { +		printf(" ?"); +
>> ramsize = sunxi_dram_init(); +	} +	if (!ramsize) { +		printf("
>> ?"); +		ramsize = sunxi_dram_init(); +	}
> 
> We have to try 3 times?  What?
> 
TLDR: only needs to be called once.

I have no idea why this is here. We use the same raminit code in
coreboot, and it works when we call it the first time.
The raminit code we had when this was written was not tuned to use
proper delays. I imagine whoever initially wrote this triple-play, was
dealing with finicky raminit code, and found out that calling it a few
times worked.
I think it's safe to remove tries 2 and 3.

>> +	/* +	 * Only clock up the CPU to full speed if we are
>> reasonably +	 * assured it's being powered with suitable core
>> voltage +	 */ +	if (!power_failed) +		clock_set_pll1(912000000);
> 
> Define that please.
> 
TLDR: This does not belong in this patch

power_failed was a flag returned by the Power Manager Unit code (PMU).
The PMU on these boards is used to ramp up the CPU voltage. You need
that to be able to get to full clock without hanging. power_failed
lets us know if something went wrong with the PMU setup and we should
leave the clocks the way they were.
I think this should be added in the patch which adds the power setup.

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-----END PGP SIGNATURE-----

[U-Boot] [PATCH v1 5/9] sunxi: generic sun7i build infrastructure.

[Ian Campbell]

Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
ldscripts" vs v2014.01.

This has been stripped back for mainlining and supports only sun7i booting via
FEL mode. These changes are not useful by themselves but are split out to make
the patch sizes more manageable.

As well as the following signed-off-by the sunxi branch shows commits to these
files authored by the following:
  Almo Nito
  Carl van Schaik
  FUKAUMI Naoki
  hehopmajieh
  j
  Sergey Lapin
  Tom Cubie

Signed-off-by: Adam Sampson <ats@offog.org>
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Emilio L?pez <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Patrick Wood <patrickhwood@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/Makefile                 |   2 +-
 arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds |  59 +++++++++++
 arch/arm/include/asm/arch-sunxi/spl.h       |  36 +++++++
 board/sunxi/Makefile                        |   1 +
 include/configs/sun7i.h                     |  41 ++++++++
 include/configs/sunxi-common.h              | 154 ++++++++++++++++++++++++++++
 6 files changed, 292 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
 create mode 100644 arch/arm/include/asm/arch-sunxi/spl.h
 create mode 100644 include/configs/sun7i.h
 create mode 100644 include/configs/sunxi-common.h

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 0467d00..71c233c 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@ obj-y	+= cache_v7.o
 obj-y	+= cpu.o
 obj-y	+= syslib.o
 
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
new file mode 100644
index 0000000..cf02300
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
@@ -0,0 +1,59 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(s_init)
+SECTIONS
+{
+ . = 0x00002000;
+ . = ALIGN(4);
+ .text :
+ {
+  *(.text.s_init)
+  *(.text*)
+ }
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+ . = ALIGN(4);
+ .data : {
+  *(.data*)
+ }
+ . = ALIGN(4);
+ . = .;
+ . = ALIGN(4);
+ .rel.dyn : {
+  __rel_dyn_start = .;
+  *(.rel*)
+  __rel_dyn_end = .;
+ }
+ .dynsym : {
+  __dynsym_start = .;
+  *(.dynsym)
+ }
+ . = ALIGN(4);
+ .note.gnu.build-id :
+ {
+	*(.note.gnu.build-id)
+ }
+ _end = .;
+ . = ALIGN(4096);
+ .mmutable : {
+  *(.mmutable)
+ }
+ .bss_start __rel_dyn_start (OVERLAY) : {
+  KEEP(*(.__bss_start));
+  __bss_base = .;
+ }
+ .bss __bss_base (OVERLAY) : {
+  *(.bss*)
+   . = ALIGN(4);
+   __bss_limit = .;
+ }
+ .bss_end __bss_limit (OVERLAY) : {
+  KEEP(*(.__bss_end));
+ }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+ /DISCARD/ : { *(.note*) }
+}
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
new file mode 100644
index 0000000..6a47d14
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -0,0 +1,36 @@
+/*
+ * This is a copy of omap3/spl.h:
+ *
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_NAND	2
+#define BOOT_DEVICE_ONE_NAND	3
+#define BOOT_DEVICE_MMC2	5 /*emmc*/
+#define BOOT_DEVICE_MMC1	6
+#define BOOT_DEVICE_XIPWAIT	7
+#define BOOT_DEVICE_MMC2_2      0xff
+#endif
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index b8c26ab..180adc9 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -26,3 +26,4 @@
 #
 
 obj-y	+= board.o
+obj-y	+= dram_cubietruck.o
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
new file mode 100644
index 0000000..4660d7b
--- /dev/null
+++ b/include/configs/sun7i.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * Configuration settings for the Allwinner A20 (sun7i) CPU
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A20 specific configuration
+ */
+#define CONFIG_SUN7I		/* sun7i SoC generation */
+
+#define CONFIG_SYS_PROMPT		"sun7i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
new file mode 100644
index 0000000..bdfc169
--- /dev/null
+++ b/include/configs/sunxi-common.h
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Configuration settings for the Allwinner sunxi series of boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SUNXI_COMMON_CONFIG_H
+#define _SUNXI_COMMON_CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ALLWINNER	/* It's a Allwinner chip */
+#define CONFIG_SUNXI		/* which is sunxi family */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+
+#define CONFIG_SYS_TEXT_BASE		0x4a000000
+
+/*
+ * Display CPU information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Serial & console */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+/* ns16550 reg in the low bits of cpu reg */
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(24000000)
+#define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
+#define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
+#define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
+#define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* 32 KiB */
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER	/* use "hush" command parser    */
+#define CONFIG_CMD_ECHO
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (256 << 20))
+#define CONFIG_SYS_LOAD_ADDR		0x50000000 /* default load address */
+
+/* standalone support */
+#define CONFIG_STANDALONE_LOAD_ADDR	0x50000000
+
+#define CONFIG_SYS_HZ			1000
+
+/* valid baudrates */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
+
+/* FLASH and environment organization */
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* 512 KiB */
+#define CONFIG_IDENT_STRING		" Allwinner Technology"
+
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_SYS_BOOT_GET_CMDLINE
+#define CONFIG_AUTO_COMPLETE
+
+#include <config_cmd_default.h>
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#define CONFIG_SPL
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds"
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi"
+#define CONFIG_SPL_TEXT_BASE		0x2000
+#define CONFIG_SPL_MAX_SIZE		0x4000		/* 16 KiB */
+/* end of 32 KiB in sram */
+#define LOW_LEVEL_SRAM_STACK		0x00008000
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#undef CONFIG_CMD_NET
+
+#define CONFIG_CONS_INDEX              1       /* UART0 */
+
+#if !defined CONFIG_ENV_IS_IN_MMC && \
+    !defined CONFIG_ENV_IS_IN_NAND && \
+    !defined CONFIG_ENV_IS_IN_FAT && \
+    !defined CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#endif /* _SUNXI_COMMON_CONFIG_H */
-- 
1.8.5.3

[U-Boot] [PATCH v1 5/9] sunxi: generic sun7i build infrastructure.

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:47AM +0000, Ian Campbell wrote:

[snip]
> +#define CONFIG_SUN7I		/* sun7i SoC generation */
[snip]
> +#define CONFIG_ALLWINNER	/* It's a Allwinner chip */
> +#define CONFIG_SUNXI		/* which is sunxi family */

Please make sure we end up using all 3 of these.  I know I spotted a
CONFIG_SUNXI in use, but I don't know about ALLWINNER or SUN7I.

> +/*
> + * Size of malloc() pool
> + * 1MB = 0x100000, 0x100000 = 1024 * 1024
> + */
> +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))

This is really really small, and precludes using UBI on NAND for
example.

> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

Not needed.

> +/* memtest works on */
> +#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (256 << 20))

Please see doc/README.memory-test

> +#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

Please use the default table.

-- 
Tom
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[U-Boot] [PATCH v1 5/9] sunxi: generic sun7i build infrastructure.

[Ian Campbell]

On Fri, 2014-03-14 at 10:17 -0400, Tom Rini wrote:
> On Fri, Mar 14, 2014 at 10:33:47AM +0000, Ian Campbell wrote:

> > +/*
> > + * Size of malloc() pool
> > + * 1MB = 0x100000, 0x100000 = 1024 * 1024
> > + */
> > +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
> 
> This is really really small, and precludes using UBI on NAND for
> example.

What is a suitable value? I see a lots of boards using 128kB or <1MB and
only a handful using more. Tegra uses 4MB -- is that a reasonable value?

Ian.

[U-Boot] [PATCH v1 5/9] sunxi: generic sun7i build infrastructure.

[Tom Rini]

On Sun, Mar 16, 2014 at 01:25:33PM +0000, Ian Campbell wrote:
> On Fri, 2014-03-14 at 10:17 -0400, Tom Rini wrote:
> > On Fri, Mar 14, 2014 at 10:33:47AM +0000, Ian Campbell wrote:
> 
> > > +/*
> > > + * Size of malloc() pool
> > > + * 1MB = 0x100000, 0x100000 = 1024 * 1024
> > > + */
> > > +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
> > 
> > This is really really small, and precludes using UBI on NAND for
> > example.
> 
> What is a suitable value? I see a lots of boards using 128kB or <1MB and
> only a handful using more. Tegra uses 4MB -- is that a reasonable value?

4MB is reasonable when you start having to worry about 4KB page NAND and
UBI.  I might have been a little harsh saying "really really small" and
1MB might be just enough to work with smaller page size NAND.

-- 
Tom
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[U-Boot] [PATCH v1 5/9] sunxi: generic sun7i build infrastructure.

[Ian Campbell]

On Mon, 2014-03-17 at 11:04 -0400, Tom Rini wrote:
> On Sun, Mar 16, 2014 at 01:25:33PM +0000, Ian Campbell wrote:
> > On Fri, 2014-03-14 at 10:17 -0400, Tom Rini wrote:
> > > On Fri, Mar 14, 2014 at 10:33:47AM +0000, Ian Campbell wrote:
> > 
> > > > +/*
> > > > + * Size of malloc() pool
> > > > + * 1MB = 0x100000, 0x100000 = 1024 * 1024
> > > > + */
> > > > +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
> > > 
> > > This is really really small, and precludes using UBI on NAND for
> > > example.
> > 
> > What is a suitable value? I see a lots of boards using 128kB or <1MB and
> > only a handful using more. Tegra uses 4MB -- is that a reasonable value?
> 
> 4MB is reasonable when you start having to worry about 4KB page NAND and
> UBI.  I might have been a little harsh saying "really really small" and
> 1MB might be just enough to work with smaller page size NAND.

Thanks, I'll go with 4MB then.

Ian.

[U-Boot] [PATCH v1 6/9] sunxi: add support for Cubietruck booting in FEL mode

[Ian Campbell]

Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
ldscripts" vs v2014.01.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
---
 board/sunxi/dram_cubietruck.c | 31 +++++++++++++++++++++++++++++++
 boards.cfg                    |  1 +
 2 files changed, 32 insertions(+)
 create mode 100644 board/sunxi/dram_cubietruck.c

diff --git a/board/sunxi/dram_cubietruck.c b/board/sunxi/dram_cubietruck.c
new file mode 100644
index 0000000..1e7c94a
--- /dev/null
+++ b/board/sunxi/dram_cubietruck.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+	.clock = 432,
+	.type = 3,
+	.rank_num = 1,
+	.density = 8192,
+	.io_width = 16,
+	.bus_width = 32,
+	.cas = 9,
+	.zq = 0x7f,
+	.odt_en = 0,
+	.size = 2048,
+	.tpr0 = 0x42d899b7,
+	.tpr1 = 0xa090,
+	.tpr2 = 0x22a00,
+	.tpr3 = 0x0,
+	.tpr4 = 0x1,
+	.tpr5 = 0x0,
+	.emr1 = 0x4,
+	.emr2 = 0x10,
+	.emr3 = 0x0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+	return dramc_init(&dram_para);
+}
diff --git a/boards.cfg b/boards.cfg
index a8336cc..6c35a40 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -353,6 +353,7 @@ Active  arm         armv7          rmobile     renesas         koelsch
 Active  arm         armv7          s5pc1xx     samsung         goni                s5p_goni                             -                                                                                                                                 Mateusz Zalega <m.zalega@samsung.com>
 Active  arm         armv7          s5pc1xx     samsung         smdkc100            smdkc100                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
 Active  arm         armv7          socfpga     altera          socfpga             socfpga_cyclone5                     -                                                                                                                                 -
+Active  arm         armv7          sunxi       -               sunxi               Cubietruck_FEL                       sun7i:CUBIETRUCK,SPL_FEL                                                                                                          -
 Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
 Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
 Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
-- 
1.8.5.3

[U-Boot] [PATCH v1 6/9] sunxi: add support for Cubietruck booting in FEL mode

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:48AM +0000, Ian Campbell wrote:

> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> ldscripts" vs v2014.01.
> 
> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>

Reviewed-by: Tom Rini <trini@ti.com>

-- 
Tom
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[U-Boot] [PATCH v1 7/9] sunxi: mmc support

[Ian Campbell]

Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
ldscripts" vs v2014.01.

As well as the following signed-off-by the sunxi branch shows commits to these
files authored by the following:
  Stefan Roese
  Tom Cubie
  yemao

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/include/asm/arch-sunxi/mmc.h |  66 ++++
 board/sunxi/board.c                   |  13 +
 drivers/mmc/Makefile                  |   1 +
 drivers/mmc/sunxi_mmc.c               | 650 ++++++++++++++++++++++++++++++++++
 include/configs/sunxi-common.h        |  11 +
 5 files changed, 741 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/mmc.h
 create mode 100755 drivers/mmc/sunxi_mmc.c

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
new file mode 100644
index 0000000..639a7fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Aaron <leafy.myeh@allwinnertech.com>
+ *
+ * MMC register definition for allwinner sunxi platform.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SUNXI_MMC_H
+#define _SUNXI_MMC_H
+
+#include <linux/types.h>
+
+struct sunxi_mmc {
+	u32 gctrl;		/* (0x00) SMC Global Control Register */
+	u32 clkcr;		/* (0x04) SMC Clock Control Register */
+	u32 timeout;		/* (0x08) SMC Time Out Register */
+	u32 width;		/* (0x0c) SMC Bus Width Register */
+	u32 blksz;		/* (0x10) SMC Block Size Register */
+	u32 bytecnt;		/* (0x14) SMC Byte Count Register */
+	u32 cmd;		/* (0x18) SMC Command Register */
+	u32 arg;		/* (0x1c) SMC Argument Register */
+	u32 resp0;		/* (0x20) SMC Response Register 0 */
+	u32 resp1;		/* (0x24) SMC Response Register 1 */
+	u32 resp2;		/* (0x28) SMC Response Register 2 */
+	u32 resp3;		/* (0x2c) SMC Response Register 3 */
+	u32 imask;		/* (0x30) SMC Interrupt Mask Register */
+	u32 mint;		/* (0x34) SMC Masked Interrupt Status Reg */
+	u32 rint;		/* (0x38) SMC Raw Interrupt Status Register */
+	u32 status;		/* (0x3c) SMC Status Register */
+	u32 ftrglevel;		/* (0x40) SMC FIFO Threshold Watermark Reg */
+	u32 funcsel;		/* (0x44) SMC Function Select Register */
+	u32 cbcr;		/* (0x48) SMC CIU Byte Count Register */
+	u32 bbcr;		/* (0x4c) SMC BIU Byte Count Register */
+	u32 dbgc;		/* (0x50) SMC Debug Enable Register */
+	u32 res0[11];		/* (0x54~0x7c) */
+	u32 dmac;		/* (0x80) SMC IDMAC Control Register */
+	u32 dlba;		/* (0x84) SMC IDMAC Descr List Base Addr Reg */
+	u32 idst;		/* (0x88) SMC IDMAC Status Register */
+	u32 idie;		/* (0x8c) SMC IDMAC Interrupt Enable Register */
+	u32 chda;		/* (0x90) */
+	u32 cbda;		/* (0x94) */
+	u32 res1[26];		/* (0x98~0xff) */
+	u32 fifo;		/* (0x100) SMC FIFO Access Address */
+};
+
+int sunxi_mmc_init(int sdc_no);
+#endif /* _SUNXI_MMC_H */
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index bffef4f..5dbcf2a 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -30,6 +30,7 @@
 #include <common.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/dram.h>
+#include <asm/arch/mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -59,6 +60,18 @@ int dram_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
+#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
+	sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+#endif
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 void sunxi_board_init(void)
 {
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index e793ed9..c695841 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
 obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
 obj-$(CONFIG_DWMMC) += dw_mmc.o
 obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
+obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
 obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
 obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
 ifdef CONFIG_SPL_BUILD
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
new file mode 100755
index 0000000..13eba76
--- /dev/null
+++ b/drivers/mmc/sunxi_mmc.c
@@ -0,0 +1,650 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Aaron <leafy.myeh@allwinnertech.com>
+ *
+ * MMC driver for allwinner sunxi platform.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+
+static void dumphex32(char *name, char *base, int len)
+{
+	__u32 i;
+
+	debug("dump %s registers:", name);
+	for (i = 0; i < len; i += 4) {
+		if (!(i & 0xf))
+			debug("\n0x%p : ", base + i);
+		debug("0x%08x ", readl(base + i));
+	}
+	debug("\n");
+}
+
+static void dumpmmcreg(struct sunxi_mmc *reg)
+{
+	debug("dump mmc registers:\n");
+	debug("gctrl     0x%08x\n", reg->gctrl);
+	debug("clkcr     0x%08x\n", reg->clkcr);
+	debug("timeout   0x%08x\n", reg->timeout);
+	debug("width     0x%08x\n", reg->width);
+	debug("blksz     0x%08x\n", reg->blksz);
+	debug("bytecnt   0x%08x\n", reg->bytecnt);
+	debug("cmd       0x%08x\n", reg->cmd);
+	debug("arg       0x%08x\n", reg->arg);
+	debug("resp0     0x%08x\n", reg->resp0);
+	debug("resp1     0x%08x\n", reg->resp1);
+	debug("resp2     0x%08x\n", reg->resp2);
+	debug("resp3     0x%08x\n", reg->resp3);
+	debug("imask     0x%08x\n", reg->imask);
+	debug("mint      0x%08x\n", reg->mint);
+	debug("rint      0x%08x\n", reg->rint);
+	debug("status    0x%08x\n", reg->status);
+	debug("ftrglevel 0x%08x\n", reg->ftrglevel);
+	debug("funcsel   0x%08x\n", reg->funcsel);
+	debug("dmac      0x%08x\n", reg->dmac);
+	debug("dlba      0x%08x\n", reg->dlba);
+	debug("idst      0x%08x\n", reg->idst);
+	debug("idie      0x%08x\n", reg->idie);
+}
+
+struct sunxi_mmc_des {
+	u32 reserved1_1:1;
+	u32 dic:1;		/* disable interrupt on completion */
+	u32 last_des:1;		/* 1-this data buffer is the last buffer */
+	u32 first_des:1;		/* 1-data buffer is the first buffer,
+				   0-data buffer contained in the next
+				   descriptor is 1st buffer */
+	u32 des_chain:1;	/* 1-the 2nd address in the descriptor is the
+				   next descriptor address */
+	u32 end_of_ring:1;	/* 1-last descriptor flag when using dual
+				   data buffer in descriptor */
+	u32 reserved1_2:24;
+	u32 card_err_sum:1;	/* transfer error flag */
+	u32 own:1;		/* des owner:1-idma owns it, 0-host owns it */
+#define SDXC_DES_NUM_SHIFT 16
+#define SDXC_DES_BUFFER_MAX_LEN	(1 << SDXC_DES_NUM_SHIFT)
+	u32 data_buf1_sz:16;
+	u32 data_buf2_sz:16;
+	u32 buf_addr_ptr1;
+	u32 buf_addr_ptr2;
+};
+
+struct sunxi_mmc_host {
+	unsigned mmc_no;
+	uint32_t *mclkreg;
+	unsigned database;
+	unsigned fatal_err;
+	unsigned mod_clk;
+	struct sunxi_mmc *reg;
+};
+
+/* support 4 mmc hosts */
+struct mmc mmc_dev[4];
+struct sunxi_mmc_host mmc_host[4];
+
+static int mmc_resource_init(int sdc_no)
+{
+	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	debug("init mmc %d resource\n", sdc_no);
+
+	switch (sdc_no) {
+	case 0:
+		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
+		mmchost->mclkreg = &ccm->sd0_clk_cfg;
+		break;
+	case 1:
+		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
+		mmchost->mclkreg = &ccm->sd1_clk_cfg;
+		break;
+	case 2:
+		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
+		mmchost->mclkreg = &ccm->sd2_clk_cfg;
+		break;
+	case 3:
+		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
+		mmchost->mclkreg = &ccm->sd3_clk_cfg;
+		break;
+	default:
+		printf("Wrong mmc number %d\n", sdc_no);
+		return -1;
+	}
+	mmchost->database = (unsigned int)mmchost->reg + 0x100;
+	mmchost->mmc_no = sdc_no;
+
+	return 0;
+}
+
+static int mmc_clk_io_on(int sdc_no)
+{
+	unsigned int rval;
+	unsigned int pll5_clk;
+	unsigned int divider;
+	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
+	static struct sunxi_gpio *gpio_c =
+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_C];
+	static struct sunxi_gpio *gpio_f =
+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_F];
+#if CONFIG_MMC1_PG
+	static struct sunxi_gpio *gpio_g =
+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_G];
+#endif
+	static struct sunxi_gpio *gpio_h =
+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_H];
+	static struct sunxi_gpio *gpio_i =
+	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_I];
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	debug("init mmc %d clock and io\n", sdc_no);
+
+	/* config gpio */
+	switch (sdc_no) {
+	case 0:
+		/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
+		writel(0x222222, &gpio_f->cfg[0]);
+		writel(0x555, &gpio_f->pull[0]);
+		writel(0xaaa, &gpio_f->drv[0]);
+		break;
+
+	case 1:
+#if CONFIG_MMC1_PG
+		/* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */
+		writel(0x444444, &gpio_g->cfg[0]);
+		writel(0x555, &gpio_g->pull[0]);
+		writel(0xaaa, &gpio_g->drv[0]);
+#else
+		/* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */
+		writel(0x55 << 24, &gpio_h->cfg[2]);
+		writel(0x5555, &gpio_h->cfg[3]);
+		writel(0x555 << 12, &gpio_h->pull[1]);
+		writel(0xaaa << 12, &gpio_h->drv[1]);
+#endif
+		break;
+
+	case 2:
+		/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
+		writel(0x33 << 24, &gpio_c->cfg[0]);
+		writel(0x3333, &gpio_c->cfg[1]);
+		writel(0x555 << 12, &gpio_c->pull[0]);
+		writel(0xaaa << 12, &gpio_c->drv[0]);
+		break;
+
+	case 3:
+		/* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
+		writel(0x2222 << 16, &gpio_i->cfg[0]);
+		writel(0x22, &gpio_i->cfg[1]);
+		writel(0x555 << 8, &gpio_i->pull[0]);
+		writel(0x555 << 8, &gpio_i->drv[0]);
+		break;
+
+	default:
+		return -1;
+	}
+
+	/* config ahb clock */
+	rval = readl(&ccm->ahb_gate0);
+	rval |= (1 << (8 + sdc_no));
+	writel(rval, &ccm->ahb_gate0);
+
+	/* config mod clock */
+	pll5_clk = clock_get_pll5();
+	if (pll5_clk > 400000000)
+		divider = 4;
+	else
+		divider = 3;
+	writel((0x1 << 31) | (0x2 << 24) | divider, mmchost->mclkreg);
+	mmchost->mod_clk = pll5_clk / (divider + 1);
+
+	dumphex32("ccmu", (char *)SUNXI_CCM_BASE, 0x100);
+	dumphex32("gpio", (char *)SUNXI_PIO_BASE, 0x100);
+	dumphex32("mmc", (char *)mmchost->reg, 0x100);
+	dumpmmcreg(mmchost->reg);
+
+	return 0;
+}
+
+static int mmc_update_clk(struct mmc *mmc)
+{
+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
+	unsigned int cmd;
+	unsigned timeout = 0xfffff;
+
+	cmd = (0x1 << 31) | (0x1 << 21) | (0x1 << 13);
+	writel(cmd, &mmchost->reg->cmd);
+	while ((readl(&mmchost->reg->cmd) & (0x1 << 31)) && timeout--);
+	if (!timeout)
+		return -1;
+
+	writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
+
+	return 0;
+}
+
+static int mmc_config_clock(struct mmc *mmc, unsigned div)
+{
+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
+	unsigned rval = readl(&mmchost->reg->clkcr);
+
+	/*
+	 * CLKCREG[7:0]: divider
+	 * CLKCREG[16]:  on/off
+	 * CLKCREG[17]:  power save
+	 */
+	/* Disable Clock */
+	rval &= ~(0x1 << 16);
+	writel(rval, &mmchost->reg->clkcr);
+	if (mmc_update_clk(mmc))
+		return -1;
+
+	/* Change Divider Factor */
+	rval &= ~(0xff);
+	rval |= div;
+	writel(rval, &mmchost->reg->clkcr);
+	if (mmc_update_clk(mmc))
+		return -1;
+	/* Re-enable Clock */
+	rval |= (0x1 << 16);
+	writel(rval, &mmchost->reg->clkcr);
+
+	if (mmc_update_clk(mmc))
+		return -1;
+
+	return 0;
+}
+
+static void mmc_set_ios(struct mmc *mmc)
+{
+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
+	unsigned int clkdiv = 0;
+
+	debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",
+	      mmc->bus_width, mmc->clock, mmchost->mod_clk);
+
+	/* Change clock first */
+	clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
+	if (mmc->clock)
+		if (mmc_config_clock(mmc, clkdiv)) {
+			mmchost->fatal_err = 1;
+			return;
+		}
+
+	/* Change bus width */
+	if (mmc->bus_width == 8)
+		writel(0x2, &mmchost->reg->width);
+	else if (mmc->bus_width == 4)
+		writel(0x1, &mmchost->reg->width);
+	else
+		writel(0x0, &mmchost->reg->width);
+}
+
+static int mmc_core_init(struct mmc *mmc)
+{
+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
+
+	/* Reset controller */
+	writel(0x7, &mmchost->reg->gctrl);
+
+	return 0;
+}
+
+static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
+{
+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
+	unsigned i;
+	unsigned byte_cnt = data->blocksize * data->blocks;
+	unsigned *buff;
+	unsigned timeout = 0xfffff;
+
+	if (data->flags & MMC_DATA_READ) {
+		buff = (unsigned int *)data->dest;
+		for (i = 0; i < (byte_cnt >> 2); i++) {
+			while (--timeout &&
+				 (readl(&mmchost->reg->status) & (0x1 << 2)));
+			if (timeout <= 0)
+				goto out;
+			buff[i] = readl(mmchost->database);
+			timeout = 0xfffff;
+		}
+	} else {
+		buff = (unsigned int *)data->src;
+		for (i = 0; i < (byte_cnt >> 2); i++) {
+			while (--timeout &&
+				 (readl(&mmchost->reg->status) & (0x1 << 3)));
+			if (timeout <= 0)
+				goto out;
+			writel(buff[i], mmchost->database);
+			timeout = 0xfffff;
+		}
+	}
+
+out:
+	if (timeout <= 0)
+		return -1;
+
+	return 0;
+}
+
+static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data)
+{
+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
+	unsigned byte_cnt = data->blocksize * data->blocks;
+	unsigned char *buff;
+	unsigned des_idx = 0;
+	unsigned buff_frag_num =
+		(byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT;
+	unsigned remain;
+	unsigned i, rval;
+	ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num);
+
+	buff = data->flags & MMC_DATA_READ ?
+	    (unsigned char *)data->dest : (unsigned char *)data->src;
+	remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
+	if (!remain)
+		remain = SDXC_DES_BUFFER_MAX_LEN;
+
+	flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
+	for (i = 0; i < buff_frag_num; i++, des_idx++) {
+		memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des));
+		pdes[des_idx].des_chain = 1;
+		pdes[des_idx].own = 1;
+		pdes[des_idx].dic = 1;
+		if (buff_frag_num > 1 && i != buff_frag_num - 1)
+			pdes[des_idx].data_buf1_sz =
+			    (SDXC_DES_BUFFER_MAX_LEN -
+			     1) & SDXC_DES_BUFFER_MAX_LEN;
+		else
+			pdes[des_idx].data_buf1_sz = remain;
+
+		pdes[des_idx].buf_addr_ptr1 =
+		    (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN;
+		if (i == 0)
+			pdes[des_idx].first_des = 1;
+
+		if (i == buff_frag_num - 1) {
+			pdes[des_idx].dic = 0;
+			pdes[des_idx].last_des = 1;
+			pdes[des_idx].end_of_ring = 1;
+			pdes[des_idx].buf_addr_ptr2 = 0;
+		} else {
+			pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1];
+		}
+		debug("frag %d, remain %d, des[%d](%08x): ",
+		      i, remain, des_idx, (u32)&pdes[des_idx]);
+		debug("[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n",
+		      (u32)((u32 *)&pdes[des_idx])[0],
+		      (u32)((u32 *)&pdes[des_idx])[1],
+		      (u32)((u32 *)&pdes[des_idx])[2],
+		      (u32)((u32 *)&pdes[des_idx])[3]);
+	}
+	flush_cache((unsigned long)pdes,
+		    sizeof(struct sunxi_mmc_des) * (des_idx + 1));
+
+	/*
+	 * GCTRLREG
+	 * GCTRL[2]     : DMA reset
+	 * GCTRL[5]     : DMA enable
+	 *
+	 * IDMACREG
+	 * IDMAC[0]     : IDMA soft reset
+	 * IDMAC[1]     : IDMA fix burst flag
+	 * IDMAC[7]     : IDMA on
+	 *
+	 * IDIECREG
+	 * IDIE[0]      : IDMA transmit interrupt flag
+	 * IDIE[1]      : IDMA receive interrupt flag
+	 */
+	rval = readl(&mmchost->reg->gctrl);
+	/* Enable DMA */
+	writel(rval | (0x1 << 5) | (0x1 << 2), &mmchost->reg->gctrl);
+	/* Reset iDMA */
+	writel((0x1 << 0), &mmchost->reg->dmac);
+	/* Enable iDMA */
+	writel((0x1 << 1) | (1 << 7), &mmchost->reg->dmac);
+	rval = readl(&mmchost->reg->idie) & (~3);
+	if (data->flags & MMC_DATA_WRITE)
+		rval |= (0x1 << 0);
+	else
+		rval |= (0x1 << 1);
+	writel(rval, &mmchost->reg->idie);
+	writel((u32) pdes, &mmchost->reg->dlba);
+	writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),
+	       &mmchost->reg->ftrglevel);
+
+	return 0;
+}
+
+static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+			struct mmc_data *data)
+{
+	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
+	unsigned int cmdval = 0x80000000;
+	signed int timeout = 0;
+	int error = 0;
+	unsigned int status = 0;
+	unsigned int usedma = 0;
+	unsigned int bytecnt = 0;
+
+	if (mmchost->fatal_err)
+		return -1;
+	if (cmd->resp_type & MMC_RSP_BUSY)
+		debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
+	if (cmd->cmdidx == 12)
+		return 0;
+
+	/*
+	 * CMDREG
+	 * CMD[5:0]     : Command index
+	 * CMD[6]       : Has response
+	 * CMD[7]       : Long response
+	 * CMD[8]       : Check response CRC
+	 * CMD[9]       : Has data
+	 * CMD[10]      : Write
+	 * CMD[11]      : Steam mode
+	 * CMD[12]      : Auto stop
+	 * CMD[13]      : Wait previous over
+	 * CMD[14]      : About cmd
+	 * CMD[15]      : Send initialization
+	 * CMD[21]      : Update clock
+	 * CMD[31]      : Load cmd
+	 */
+	if (!cmd->cmdidx)
+		cmdval |= (0x1 << 15);
+	if (cmd->resp_type & MMC_RSP_PRESENT)
+		cmdval |= (0x1 << 6);
+	if (cmd->resp_type & MMC_RSP_136)
+		cmdval |= (0x1 << 7);
+	if (cmd->resp_type & MMC_RSP_CRC)
+		cmdval |= (0x1 << 8);
+
+	if (data) {
+		if ((u32) data->dest & 0x3) {
+			error = -1;
+			goto out;
+		}
+
+		cmdval |= (0x1 << 9) | (0x1 << 13);
+		if (data->flags & MMC_DATA_WRITE)
+			cmdval |= (0x1 << 10);
+		if (data->blocks > 1)
+			cmdval |= (0x1 << 12);
+		writel(data->blocksize, &mmchost->reg->blksz);
+		writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
+	}
+
+	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
+	      cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
+	writel(cmd->cmdarg, &mmchost->reg->arg);
+
+	if (!data)
+		writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
+
+	/*
+	 * transfer data and check status
+	 * STATREG[2] : FIFO empty
+	 * STATREG[3] : FIFO full
+	 */
+	if (data) {
+		int ret = 0;
+
+		bytecnt = data->blocksize * data->blocks;
+		debug("trans data %d bytes\n", bytecnt);
+#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD)
+		if (bytecnt > 64) {
+#else
+		if (0) {
+#endif
+			usedma = 1;
+			writel(readl(&mmchost->reg->gctrl) & ~(0x1 << 31),
+			       &mmchost->reg->gctrl);
+			ret = mmc_trans_data_by_dma(mmc, data);
+			writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
+		} else {
+			writel(readl(&mmchost->reg->gctrl) | 0x1 << 31,
+			       &mmchost->reg->gctrl);
+			writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
+			ret = mmc_trans_data_by_cpu(mmc, data);
+		}
+		if (ret) {
+			error = readl(&mmchost->reg->rint) & 0xbfc2;
+			error = TIMEOUT;
+			goto out;
+		}
+	}
+
+	timeout = 0xfffff;
+	do {
+		status = readl(&mmchost->reg->rint);
+		if (!timeout-- || (status & 0xbfc2)) {
+			error = status & 0xbfc2;
+			debug("cmd timeout %x\n", error);
+			error = TIMEOUT;
+			goto out;
+		}
+	} while (!(status & 0x4));
+
+	if (data) {
+		unsigned done = 0;
+		timeout = usedma ? 0xffff * bytecnt : 0xffff;
+		debug("cacl timeout %x\n", timeout);
+		do {
+			status = readl(&mmchost->reg->rint);
+			if (!timeout-- || (status & 0xbfc2)) {
+				error = status & 0xbfc2;
+				debug("data timeout %x\n", error);
+				error = TIMEOUT;
+				goto out;
+			}
+			if (data->blocks > 1)
+				done = status & (0x1 << 14);
+			else
+				done = status & (0x1 << 3);
+		} while (!done);
+	}
+
+	if (cmd->resp_type & MMC_RSP_BUSY) {
+		timeout = 0xfffff;
+		do {
+			status = readl(&mmchost->reg->status);
+			if (!timeout--) {
+				debug("busy timeout\n");
+				error = TIMEOUT;
+				goto out;
+			}
+		} while (status & (1 << 9));
+	}
+
+	if (cmd->resp_type & MMC_RSP_136) {
+		cmd->response[0] = readl(&mmchost->reg->resp3);
+		cmd->response[1] = readl(&mmchost->reg->resp2);
+		cmd->response[2] = readl(&mmchost->reg->resp1);
+		cmd->response[3] = readl(&mmchost->reg->resp0);
+		debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
+		      cmd->response[3], cmd->response[2],
+		      cmd->response[1], cmd->response[0]);
+	} else {
+		cmd->response[0] = readl(&mmchost->reg->resp0);
+		debug("mmc resp 0x%08x\n", cmd->response[0]);
+	}
+out:
+	if (data && usedma) {
+		/* IDMASTAREG
+		 * IDST[0] : idma tx int
+		 * IDST[1] : idma rx int
+		 * IDST[2] : idma fatal bus error
+		 * IDST[4] : idma descriptor invalid
+		 * IDST[5] : idma error summary
+		 * IDST[8] : idma normal interrupt sumary
+		 * IDST[9] : idma abnormal interrupt sumary
+		 */
+		status = readl(&mmchost->reg->idst);
+		writel(status, &mmchost->reg->idst);
+		writel(0, &mmchost->reg->idie);
+		writel(0, &mmchost->reg->dmac);
+		writel(readl(&mmchost->reg->gctrl) & ~(0x1 << 5),
+		       &mmchost->reg->gctrl);
+	}
+	if (error < 0) {
+		writel(0x7, &mmchost->reg->gctrl);
+		mmc_update_clk(mmc);
+	}
+	writel(0xffffffff, &mmchost->reg->rint);
+	writel(readl(&mmchost->reg->gctrl) | (1 << 1), &mmchost->reg->gctrl);
+
+	return error;
+}
+
+int sunxi_mmc_init(int sdc_no)
+{
+	struct mmc *mmc;
+
+	memset(&mmc_dev[sdc_no], 0, sizeof(struct mmc));
+	memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
+	mmc = &mmc_dev[sdc_no];
+
+	sprintf(mmc->name, "SUNXI SD/MMC");
+	mmc->priv = &mmc_host[sdc_no];
+	mmc->send_cmd = mmc_send_cmd;
+	mmc->set_ios = mmc_set_ios;
+	mmc->init = mmc_core_init;
+
+	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+	mmc->host_caps = MMC_MODE_4BIT;
+	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+	mmc->f_min = 400000;
+	mmc->f_max = 52000000;
+
+	mmc_resource_init(sdc_no);
+	mmc_clk_io_on(sdc_no);
+
+	mmc_register(mmc);
+
+	return 0;
+}
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index bdfc169..1afdeb2 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -74,6 +74,16 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_CMDLINE_EDITING
 
+/* mmc config */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_MMC_SUNXI
+#define CONFIG_MMC_SUNXI_SLOT		0
+#define CONFIG_MMC_SUNXI_USE_DMA
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
+
 /*
  * Size of malloc() pool
  * 1MB = 0x100000, 0x100000 = 1024 * 1024
@@ -118,6 +128,7 @@
 #define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* 512 KiB */
 #define CONFIG_IDENT_STRING		" Allwinner Technology"
 
+#define CONFIG_ENV_OFFSET		(544 << 10) /* (8 + 24 + 512) KiB */
 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 
 #define CONFIG_BOOTDELAY	3
-- 
1.8.5.3

[U-Boot] [PATCH v1 7/9] sunxi: mmc support

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:49AM +0000, Ian Campbell wrote:

> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> ldscripts" vs v2014.01.
> 
> As well as the following signed-off-by the sunxi branch shows commits to these
> files authored by the following:
>   Stefan Roese
>   Tom Cubie
>   yemao
> 
> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
> Signed-off-by: Luke Leighton <lkcl@lkcl.net>
> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>

Just the general problems.  Pantelis?

-- 
Tom
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[U-Boot] [PATCH v1 7/9] sunxi: mmc support

[Pantelis Antoniou]

Hi Ian,

On Mar 14, 2014, at 12:33 PM, Ian Campbell wrote:

> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> ldscripts" vs v2014.01.
> 
> As well as the following signed-off-by the sunxi branch shows commits to these
> files authored by the following:
>  Stefan Roese
>  Tom Cubie
>  yemao
> 
> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
> Signed-off-by: Luke Leighton <lkcl@lkcl.net>
> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
> Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
> ---
> arch/arm/include/asm/arch-sunxi/mmc.h |  66 ++++
> board/sunxi/board.c                   |  13 +
> drivers/mmc/Makefile                  |   1 +
> drivers/mmc/sunxi_mmc.c               | 650 ++++++++++++++++++++++++++++++++++
> include/configs/sunxi-common.h        |  11 +
> 5 files changed, 741 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-sunxi/mmc.h
> create mode 100755 drivers/mmc/sunxi_mmc.c
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
> new file mode 100644
> index 0000000..639a7fc
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
> @@ -0,0 +1,66 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Aaron <leafy.myeh@allwinnertech.com>
> + *
> + * MMC register definition for allwinner sunxi platform.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef _SUNXI_MMC_H
> +#define _SUNXI_MMC_H
> +
> +#include <linux/types.h>
> +
> +struct sunxi_mmc {
> +	u32 gctrl;		/* (0x00) SMC Global Control Register */
> +	u32 clkcr;		/* (0x04) SMC Clock Control Register */
> +	u32 timeout;		/* (0x08) SMC Time Out Register */
> +	u32 width;		/* (0x0c) SMC Bus Width Register */
> +	u32 blksz;		/* (0x10) SMC Block Size Register */
> +	u32 bytecnt;		/* (0x14) SMC Byte Count Register */
> +	u32 cmd;		/* (0x18) SMC Command Register */
> +	u32 arg;		/* (0x1c) SMC Argument Register */
> +	u32 resp0;		/* (0x20) SMC Response Register 0 */
> +	u32 resp1;		/* (0x24) SMC Response Register 1 */
> +	u32 resp2;		/* (0x28) SMC Response Register 2 */
> +	u32 resp3;		/* (0x2c) SMC Response Register 3 */
> +	u32 imask;		/* (0x30) SMC Interrupt Mask Register */
> +	u32 mint;		/* (0x34) SMC Masked Interrupt Status Reg */
> +	u32 rint;		/* (0x38) SMC Raw Interrupt Status Register */
> +	u32 status;		/* (0x3c) SMC Status Register */
> +	u32 ftrglevel;		/* (0x40) SMC FIFO Threshold Watermark Reg */
> +	u32 funcsel;		/* (0x44) SMC Function Select Register */
> +	u32 cbcr;		/* (0x48) SMC CIU Byte Count Register */
> +	u32 bbcr;		/* (0x4c) SMC BIU Byte Count Register */
> +	u32 dbgc;		/* (0x50) SMC Debug Enable Register */
> +	u32 res0[11];		/* (0x54~0x7c) */
> +	u32 dmac;		/* (0x80) SMC IDMAC Control Register */
> +	u32 dlba;		/* (0x84) SMC IDMAC Descr List Base Addr Reg */
> +	u32 idst;		/* (0x88) SMC IDMAC Status Register */
> +	u32 idie;		/* (0x8c) SMC IDMAC Interrupt Enable Register */
> +	u32 chda;		/* (0x90) */
> +	u32 cbda;		/* (0x94) */
> +	u32 res1[26];		/* (0x98~0xff) */
> +	u32 fifo;		/* (0x100) SMC FIFO Access Address */
> +};
> +
> +int sunxi_mmc_init(int sdc_no);
> +#endif /* _SUNXI_MMC_H */
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index bffef4f..5dbcf2a 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -30,6 +30,7 @@
> #include <common.h>
> #include <asm/arch/clock.h>
> #include <asm/arch/dram.h>
> +#include <asm/arch/mmc.h>
> 
> DECLARE_GLOBAL_DATA_PTR;
> 
> @@ -59,6 +60,18 @@ int dram_init(void)
> 	return 0;
> }
> 
> +#ifdef CONFIG_GENERIC_MMC
> +int board_mmc_init(bd_t *bis)
> +{
> +	sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
> +#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
> +	sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
> +#endif
> +
> +	return 0;
> +}
> +#endif
> +
> #ifdef CONFIG_SPL_BUILD
> void sunxi_board_init(void)
> {
> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> index e793ed9..c695841 100644
> --- a/drivers/mmc/Makefile
> +++ b/drivers/mmc/Makefile
> @@ -27,6 +27,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
> obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
> obj-$(CONFIG_DWMMC) += dw_mmc.o
> obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
> +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
> obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
> obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
> ifdef CONFIG_SPL_BUILD
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> new file mode 100755
> index 0000000..13eba76
> --- /dev/null
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -0,0 +1,650 @@
> +/*
> + * (C) Copyright 2007-2011
> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
> + * Aaron <leafy.myeh@allwinnertech.com>
> + *
> + * MMC driver for allwinner sunxi platform.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <mmc.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/mmc.h>
> +
> +static void dumphex32(char *name, char *base, int len)
> +{
> +	__u32 i;
> +
> +	debug("dump %s registers:", name);
> +	for (i = 0; i < len; i += 4) {
> +		if (!(i & 0xf))
> +			debug("\n0x%p : ", base + i);
> +		debug("0x%08x ", readl(base + i));
> +	}
> +	debug("\n");
> +}
> +
> +static void dumpmmcreg(struct sunxi_mmc *reg)
> +{
> +	debug("dump mmc registers:\n");
> +	debug("gctrl     0x%08x\n", reg->gctrl);
> +	debug("clkcr     0x%08x\n", reg->clkcr);
> +	debug("timeout   0x%08x\n", reg->timeout);
> +	debug("width     0x%08x\n", reg->width);
> +	debug("blksz     0x%08x\n", reg->blksz);
> +	debug("bytecnt   0x%08x\n", reg->bytecnt);
> +	debug("cmd       0x%08x\n", reg->cmd);
> +	debug("arg       0x%08x\n", reg->arg);
> +	debug("resp0     0x%08x\n", reg->resp0);
> +	debug("resp1     0x%08x\n", reg->resp1);
> +	debug("resp2     0x%08x\n", reg->resp2);
> +	debug("resp3     0x%08x\n", reg->resp3);
> +	debug("imask     0x%08x\n", reg->imask);
> +	debug("mint      0x%08x\n", reg->mint);
> +	debug("rint      0x%08x\n", reg->rint);
> +	debug("status    0x%08x\n", reg->status);
> +	debug("ftrglevel 0x%08x\n", reg->ftrglevel);
> +	debug("funcsel   0x%08x\n", reg->funcsel);
> +	debug("dmac      0x%08x\n", reg->dmac);
> +	debug("dlba      0x%08x\n", reg->dlba);
> +	debug("idst      0x%08x\n", reg->idst);
> +	debug("idie      0x%08x\n", reg->idie);
> +}

^^^ #ifdef DEBUG here?
> +
> +struct sunxi_mmc_des {
> +	u32 reserved1_1:1;
> +	u32 dic:1;		/* disable interrupt on completion */
> +	u32 last_des:1;		/* 1-this data buffer is the last buffer */
> +	u32 first_des:1;		/* 1-data buffer is the first buffer,
> +				   0-data buffer contained in the next
> +				   descriptor is 1st buffer */
> +	u32 des_chain:1;	/* 1-the 2nd address in the descriptor is the
> +				   next descriptor address */
> +	u32 end_of_ring:1;	/* 1-last descriptor flag when using dual
> +				   data buffer in descriptor */
> +	u32 reserved1_2:24;
> +	u32 card_err_sum:1;	/* transfer error flag */
> +	u32 own:1;		/* des owner:1-idma owns it, 0-host owns it */
> +#define SDXC_DES_NUM_SHIFT 16
> +#define SDXC_DES_BUFFER_MAX_LEN	(1 << SDXC_DES_NUM_SHIFT)
> +	u32 data_buf1_sz:16;
> +	u32 data_buf2_sz:16;
> +	u32 buf_addr_ptr1;
> +	u32 buf_addr_ptr2;
> +};
> +
> +struct sunxi_mmc_host {
> +	unsigned mmc_no;
> +	uint32_t *mclkreg;
> +	unsigned database;
> +	unsigned fatal_err;
> +	unsigned mod_clk;
> +	struct sunxi_mmc *reg;
> +};
> +
> +/* support 4 mmc hosts */
> +struct mmc mmc_dev[4];
> +struct sunxi_mmc_host mmc_host[4];
> +

^ hosts & mmc structs can be allocated even for SPL now

> +static int mmc_resource_init(int sdc_no)
> +{
> +	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
> +	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> +
> +	debug("init mmc %d resource\n", sdc_no);
> +
> +	switch (sdc_no) {
> +	case 0:
> +		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
> +		mmchost->mclkreg = &ccm->sd0_clk_cfg;
> +		break;
> +	case 1:
> +		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
> +		mmchost->mclkreg = &ccm->sd1_clk_cfg;
> +		break;
> +	case 2:
> +		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
> +		mmchost->mclkreg = &ccm->sd2_clk_cfg;
> +		break;
> +	case 3:
> +		mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
> +		mmchost->mclkreg = &ccm->sd3_clk_cfg;
> +		break;
> +	default:
> +		printf("Wrong mmc number %d\n", sdc_no);
> +		return -1;
> +	}
> +	mmchost->database = (unsigned int)mmchost->reg + 0x100;
> +	mmchost->mmc_no = sdc_no;
> +
> +	return 0;
> +}
> +
> +static int mmc_clk_io_on(int sdc_no)
> +{
> +	unsigned int rval;
> +	unsigned int pll5_clk;
> +	unsigned int divider;
> +	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
> +	static struct sunxi_gpio *gpio_c =
> +	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_C];
> +	static struct sunxi_gpio *gpio_f =
> +	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_F];
> +#if CONFIG_MMC1_PG
> +	static struct sunxi_gpio *gpio_g =
> +	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_G];
> +#endif
> +	static struct sunxi_gpio *gpio_h =
> +	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_H];
> +	static struct sunxi_gpio *gpio_i =
> +	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_I];
> +	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> +

^ Castings are ugly; rework with a temporary variable.

> +	debug("init mmc %d clock and io\n", sdc_no);
> +
> +	/* config gpio */
> +	switch (sdc_no) {
> +	case 0:
> +		/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
> +		writel(0x222222, &gpio_f->cfg[0]);
> +		writel(0x555, &gpio_f->pull[0]);
> +		writel(0xaaa, &gpio_f->drv[0]);
> +		break;
> +
> +	case 1:
> +#if CONFIG_MMC1_PG
> +		/* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */
> +		writel(0x444444, &gpio_g->cfg[0]);
> +		writel(0x555, &gpio_g->pull[0]);
> +		writel(0xaaa, &gpio_g->drv[0]);
> +#else
> +		/* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */
> +		writel(0x55 << 24, &gpio_h->cfg[2]);
> +		writel(0x5555, &gpio_h->cfg[3]);
> +		writel(0x555 << 12, &gpio_h->pull[1]);
> +		writel(0xaaa << 12, &gpio_h->drv[1]);
> +#endif
> +		break;
> +
> +	case 2:
> +		/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
> +		writel(0x33 << 24, &gpio_c->cfg[0]);
> +		writel(0x3333, &gpio_c->cfg[1]);
> +		writel(0x555 << 12, &gpio_c->pull[0]);
> +		writel(0xaaa << 12, &gpio_c->drv[0]);
> +		break;
> +
> +	case 3:
> +		/* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
> +		writel(0x2222 << 16, &gpio_i->cfg[0]);
> +		writel(0x22, &gpio_i->cfg[1]);
> +		writel(0x555 << 8, &gpio_i->pull[0]);
> +		writel(0x555 << 8, &gpio_i->drv[0]);
> +		break;
> +
> +	default:
> +		return -1;
> +	}
> +

Lots of magic constants. I have no idea what's going on here.
Use a few defines.

> +	/* config ahb clock */
> +	rval = readl(&ccm->ahb_gate0);
> +	rval |= (1 << (8 + sdc_no));
> +	writel(rval, &ccm->ahb_gate0);
> +
> +	/* config mod clock */
> +	pll5_clk = clock_get_pll5();
> +	if (pll5_clk > 400000000)
> +		divider = 4;
> +	else
> +		divider = 3;
> +	writel((0x1 << 31) | (0x2 << 24) | divider, mmchost->mclkreg);
> +	mmchost->mod_clk = pll5_clk / (divider + 1);
> +
> +	dumphex32("ccmu", (char *)SUNXI_CCM_BASE, 0x100);
> +	dumphex32("gpio", (char *)SUNXI_PIO_BASE, 0x100);
> +	dumphex32("mmc", (char *)mmchost->reg, 0x100);
> +	dumpmmcreg(mmchost->reg);
> +
> +	return 0;
> +}
> +
> +static int mmc_update_clk(struct mmc *mmc)
> +{
> +	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
> +	unsigned int cmd;
> +	unsigned timeout = 0xfffff;
> +
> +	cmd = (0x1 << 31) | (0x1 << 21) | (0x1 << 13);
> +	writel(cmd, &mmchost->reg->cmd);
> +	while ((readl(&mmchost->reg->cmd) & (0x1 << 31)) && timeout--);
> +	if (!timeout)
> +		return -1;
> +

^ Eeek! Use udelay and a time based timeout. 

> +	writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
> +

^ Same here - Not even a timeout?

> +	return 0;
> +}
> +
> +static int mmc_config_clock(struct mmc *mmc, unsigned div)
> +{
> +	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
> +	unsigned rval = readl(&mmchost->reg->clkcr);
> +
> +	/*
> +	 * CLKCREG[7:0]: divider
> +	 * CLKCREG[16]:  on/off
> +	 * CLKCREG[17]:  power save
> +	 */
> +	/* Disable Clock */
> +	rval &= ~(0x1 << 16);
> +	writel(rval, &mmchost->reg->clkcr);
> +	if (mmc_update_clk(mmc))
> +		return -1;
> +
> +	/* Change Divider Factor */
> +	rval &= ~(0xff);
> +	rval |= div;
> +	writel(rval, &mmchost->reg->clkcr);
> +	if (mmc_update_clk(mmc))
> +		return -1;
> +	/* Re-enable Clock */
> +	rval |= (0x1 << 16);

#define ?
> +	writel(rval, &mmchost->reg->clkcr);
> +
> +	if (mmc_update_clk(mmc))
> +		return -1;
> +
> +	return 0;
> +}
> +
> +static void mmc_set_ios(struct mmc *mmc)
> +{
> +	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
> +	unsigned int clkdiv = 0;
> +
> +	debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",
> +	      mmc->bus_width, mmc->clock, mmchost->mod_clk);
> +
> +	/* Change clock first */
> +	clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
> +	if (mmc->clock)
> +		if (mmc_config_clock(mmc, clkdiv)) {
> +			mmchost->fatal_err = 1;
> +			return;
> +		}
> +

Ambiguous formatting. Use { }

> +	/* Change bus width */
> +	if (mmc->bus_width == 8)
> +		writel(0x2, &mmchost->reg->width);
> +	else if (mmc->bus_width == 4)
> +		writel(0x1, &mmchost->reg->width);
> +	else
> +		writel(0x0, &mmchost->reg->width);
> +}
> +
> +static int mmc_core_init(struct mmc *mmc)
> +{
> +	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
> +
> +	/* Reset controller */
> +	writel(0x7, &mmchost->reg->gctrl);
> +

Magic value again.

> +	return 0;
> +}
> +
> +static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
> +{
> +	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
> +	unsigned i;
> +	unsigned byte_cnt = data->blocksize * data->blocks;
> +	unsigned *buff;
> +	unsigned timeout = 0xfffff;
> +
> +	if (data->flags & MMC_DATA_READ) {
> +		buff = (unsigned int *)data->dest;
> +		for (i = 0; i < (byte_cnt >> 2); i++) {
> +			while (--timeout &&
> +				 (readl(&mmchost->reg->status) & (0x1 << 2)));
> +			if (timeout <= 0)
> +				goto out;
> +			buff[i] = readl(mmchost->database);
> +			timeout = 0xfffff;
> +		}
> +	} else {
> +		buff = (unsigned int *)data->src;
> +		for (i = 0; i < (byte_cnt >> 2); i++) {
> +			while (--timeout &&
> +				 (readl(&mmchost->reg->status) & (0x1 << 3)));
> +			if (timeout <= 0)
> +				goto out;
> +			writel(buff[i], mmchost->database);
> +			timeout = 0xfffff;
> +		}
> +	}
> +

^ Timeouts using time values? udelay? See above.

> +out:
> +	if (timeout <= 0)
> +		return -1;
> +
> +	return 0;
> +}
> +
> +static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data)
> +{
> +	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
> +	unsigned byte_cnt = data->blocksize * data->blocks;
> +	unsigned char *buff;
> +	unsigned des_idx = 0;
> +	unsigned buff_frag_num =
> +		(byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT;
> +	unsigned remain;
> +	unsigned i, rval;
> +	ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num);
> +
> +	buff = data->flags & MMC_DATA_READ ?
> +	    (unsigned char *)data->dest : (unsigned char *)data->src;
> +	remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
> +	if (!remain)
> +		remain = SDXC_DES_BUFFER_MAX_LEN;
> +
> +	flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
> +	for (i = 0; i < buff_frag_num; i++, des_idx++) {
> +		memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des));
> +		pdes[des_idx].des_chain = 1;
> +		pdes[des_idx].own = 1;
> +		pdes[des_idx].dic = 1;
> +		if (buff_frag_num > 1 && i != buff_frag_num - 1)
> +			pdes[des_idx].data_buf1_sz =
> +			    (SDXC_DES_BUFFER_MAX_LEN -
> +			     1) & SDXC_DES_BUFFER_MAX_LEN;
> +		else
> +			pdes[des_idx].data_buf1_sz = remain;
> +
> +		pdes[des_idx].buf_addr_ptr1 =
> +		    (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN;
> +		if (i == 0)
> +			pdes[des_idx].first_des = 1;
> +
> +		if (i == buff_frag_num - 1) {
> +			pdes[des_idx].dic = 0;
> +			pdes[des_idx].last_des = 1;
> +			pdes[des_idx].end_of_ring = 1;
> +			pdes[des_idx].buf_addr_ptr2 = 0;
> +		} else {
> +			pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1];
> +		}
> +		debug("frag %d, remain %d, des[%d](%08x): ",
> +		      i, remain, des_idx, (u32)&pdes[des_idx]);
> +		debug("[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n",
> +		      (u32)((u32 *)&pdes[des_idx])[0],
> +		      (u32)((u32 *)&pdes[des_idx])[1],
> +		      (u32)((u32 *)&pdes[des_idx])[2],
> +		      (u32)((u32 *)&pdes[des_idx])[3]);
> +	}
> +	flush_cache((unsigned long)pdes,
> +		    sizeof(struct sunxi_mmc_des) * (des_idx + 1));
> +
> +	/*
> +	 * GCTRLREG
> +	 * GCTRL[2]     : DMA reset
> +	 * GCTRL[5]     : DMA enable
> +	 *
> +	 * IDMACREG
> +	 * IDMAC[0]     : IDMA soft reset
> +	 * IDMAC[1]     : IDMA fix burst flag
> +	 * IDMAC[7]     : IDMA on
> +	 *
> +	 * IDIECREG
> +	 * IDIE[0]      : IDMA transmit interrupt flag
> +	 * IDIE[1]      : IDMA receive interrupt flag
> +	 */
> +	rval = readl(&mmchost->reg->gctrl);
> +	/* Enable DMA */
> +	writel(rval | (0x1 << 5) | (0x1 << 2), &mmchost->reg->gctrl);
> +	/* Reset iDMA */
> +	writel((0x1 << 0), &mmchost->reg->dmac);
> +	/* Enable iDMA */
> +	writel((0x1 << 1) | (1 << 7), &mmchost->reg->dmac);
> +	rval = readl(&mmchost->reg->idie) & (~3);
> +	if (data->flags & MMC_DATA_WRITE)
> +		rval |= (0x1 << 0);
> +	else
> +		rval |= (0x1 << 1);
> +	writel(rval, &mmchost->reg->idie);
> +	writel((u32) pdes, &mmchost->reg->dlba);
> +	writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),
> +	       &mmchost->reg->ftrglevel);
> +

^ #define again?

> +	return 0;
> +}
> +
> +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
> +			struct mmc_data *data)
> +{
> +	struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
> +	unsigned int cmdval = 0x80000000;
> +	signed int timeout = 0;
> +	int error = 0;
> +	unsigned int status = 0;
> +	unsigned int usedma = 0;
> +	unsigned int bytecnt = 0;
> +
> +	if (mmchost->fatal_err)
> +		return -1;
> +	if (cmd->resp_type & MMC_RSP_BUSY)
> +		debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
> +	if (cmd->cmdidx == 12)
> +		return 0;
> +
> +	/*
> +	 * CMDREG
> +	 * CMD[5:0]     : Command index
> +	 * CMD[6]       : Has response
> +	 * CMD[7]       : Long response
> +	 * CMD[8]       : Check response CRC
> +	 * CMD[9]       : Has data
> +	 * CMD[10]      : Write
> +	 * CMD[11]      : Steam mode
> +	 * CMD[12]      : Auto stop
> +	 * CMD[13]      : Wait previous over
> +	 * CMD[14]      : About cmd
> +	 * CMD[15]      : Send initialization
> +	 * CMD[21]      : Update clock
> +	 * CMD[31]      : Load cmd
> +	 */
> +	if (!cmd->cmdidx)
> +		cmdval |= (0x1 << 15);
> +	if (cmd->resp_type & MMC_RSP_PRESENT)
> +		cmdval |= (0x1 << 6);
> +	if (cmd->resp_type & MMC_RSP_136)
> +		cmdval |= (0x1 << 7);
> +	if (cmd->resp_type & MMC_RSP_CRC)
> +		cmdval |= (0x1 << 8);
> +
> +	if (data) {
> +		if ((u32) data->dest & 0x3) {
> +			error = -1;
> +			goto out;
> +		}
> +
> +		cmdval |= (0x1 << 9) | (0x1 << 13);
> +		if (data->flags & MMC_DATA_WRITE)
> +			cmdval |= (0x1 << 10);
> +		if (data->blocks > 1)
> +			cmdval |= (0x1 << 12);
> +		writel(data->blocksize, &mmchost->reg->blksz);
> +		writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
> +	}
> +
> +	debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
> +	      cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
> +	writel(cmd->cmdarg, &mmchost->reg->arg);
> +
> +	if (!data)
> +		writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
> +
> +	/*
> +	 * transfer data and check status
> +	 * STATREG[2] : FIFO empty
> +	 * STATREG[3] : FIFO full
> +	 */
> +	if (data) {
> +		int ret = 0;
> +
> +		bytecnt = data->blocksize * data->blocks;
> +		debug("trans data %d bytes\n", bytecnt);
> +#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD)
> +		if (bytecnt > 64) {
> +#else
> +		if (0) {
> +#endif
> +			usedma = 1;
> +			writel(readl(&mmchost->reg->gctrl) & ~(0x1 << 31),
> +			       &mmchost->reg->gctrl);
> +			ret = mmc_trans_data_by_dma(mmc, data);
> +			writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
> +		} else {
> +			writel(readl(&mmchost->reg->gctrl) | 0x1 << 31,
> +			       &mmchost->reg->gctrl);
> +			writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
> +			ret = mmc_trans_data_by_cpu(mmc, data);
> +		}
> +		if (ret) {
> +			error = readl(&mmchost->reg->rint) & 0xbfc2;
> +			error = TIMEOUT;
> +			goto out;
> +		}
> +	}
> +
> +	timeout = 0xfffff;
> +	do {
> +		status = readl(&mmchost->reg->rint);
> +		if (!timeout-- || (status & 0xbfc2)) {
> +			error = status & 0xbfc2;
> +			debug("cmd timeout %x\n", error);
> +			error = TIMEOUT;
> +			goto out;
> +		}

^ Again timeouts without using time values.

> +	} while (!(status & 0x4));
> +
> +	if (data) {
> +		unsigned done = 0;
> +		timeout = usedma ? 0xffff * bytecnt : 0xffff;
> +		debug("cacl timeout %x\n", timeout);
> +		do {
> +			status = readl(&mmchost->reg->rint);
> +			if (!timeout-- || (status & 0xbfc2)) {
> +				error = status & 0xbfc2;
> +				debug("data timeout %x\n", error);
> +				error = TIMEOUT;
> +				goto out;
> +			}
> +			if (data->blocks > 1)
> +				done = status & (0x1 << 14);
> +			else
> +				done = status & (0x1 << 3);

^ Timeouts?

> +		} while (!done);
> +	}
> +
> +	if (cmd->resp_type & MMC_RSP_BUSY) {
> +		timeout = 0xfffff;
> +		do {
> +			status = readl(&mmchost->reg->status);
> +			if (!timeout--) {
> +				debug("busy timeout\n");
> +				error = TIMEOUT;
> +				goto out;
> +			}
> +		} while (status & (1 << 9));
^ You get the idea... Timeouts. And #defines

> +	}
> +
> +	if (cmd->resp_type & MMC_RSP_136) {
> +		cmd->response[0] = readl(&mmchost->reg->resp3);
> +		cmd->response[1] = readl(&mmchost->reg->resp2);
> +		cmd->response[2] = readl(&mmchost->reg->resp1);
> +		cmd->response[3] = readl(&mmchost->reg->resp0);
> +		debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
> +		      cmd->response[3], cmd->response[2],
> +		      cmd->response[1], cmd->response[0]);
> +	} else {
> +		cmd->response[0] = readl(&mmchost->reg->resp0);
> +		debug("mmc resp 0x%08x\n", cmd->response[0]);
> +	}
> +out:
> +	if (data && usedma) {
> +		/* IDMASTAREG
> +		 * IDST[0] : idma tx int
> +		 * IDST[1] : idma rx int
> +		 * IDST[2] : idma fatal bus error
> +		 * IDST[4] : idma descriptor invalid
> +		 * IDST[5] : idma error summary
> +		 * IDST[8] : idma normal interrupt sumary
> +		 * IDST[9] : idma abnormal interrupt sumary
> +		 */
> +		status = readl(&mmchost->reg->idst);
> +		writel(status, &mmchost->reg->idst);
> +		writel(0, &mmchost->reg->idie);
> +		writel(0, &mmchost->reg->dmac);
> +		writel(readl(&mmchost->reg->gctrl) & ~(0x1 << 5),
> +		       &mmchost->reg->gctrl);
> +	}
> +	if (error < 0) {
> +		writel(0x7, &mmchost->reg->gctrl);
> +		mmc_update_clk(mmc);
> +	}
> +	writel(0xffffffff, &mmchost->reg->rint);
> +	writel(readl(&mmchost->reg->gctrl) | (1 << 1), &mmchost->reg->gctrl);
> +
> +	return error;
> +}
> +
> +int sunxi_mmc_init(int sdc_no)
> +{
> +	struct mmc *mmc;
> +
> +	memset(&mmc_dev[sdc_no], 0, sizeof(struct mmc));
> +	memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
> +	mmc = &mmc_dev[sdc_no];
> +
> +	sprintf(mmc->name, "SUNXI SD/MMC");
> +	mmc->priv = &mmc_host[sdc_no];
> +	mmc->send_cmd = mmc_send_cmd;
> +	mmc->set_ios = mmc_set_ios;
> +	mmc->init = mmc_core_init;
> +
> +	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
> +	mmc->host_caps = MMC_MODE_4BIT;
> +	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
> +
> +	mmc->f_min = 400000;
> +	mmc->f_max = 52000000;
> +
> +	mmc_resource_init(sdc_no);
> +	mmc_clk_io_on(sdc_no);
> +
> +	mmc_register(mmc);
> +

^ The mmc_registeration sequence has changed, but not landed at master yet.

> +	return 0;
> +}
> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
> index bdfc169..1afdeb2 100644
> --- a/include/configs/sunxi-common.h
> +++ b/include/configs/sunxi-common.h
> @@ -74,6 +74,16 @@
> #define CONFIG_INITRD_TAG
> #define CONFIG_CMDLINE_EDITING
> 
> +/* mmc config */
> +#define CONFIG_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_CMD_MMC
> +#define CONFIG_MMC_SUNXI
> +#define CONFIG_MMC_SUNXI_SLOT		0
> +#define CONFIG_MMC_SUNXI_USE_DMA
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
> +
> /*
>  * Size of malloc() pool
>  * 1MB = 0x100000, 0x100000 = 1024 * 1024
> @@ -118,6 +128,7 @@
> #define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* 512 KiB */
> #define CONFIG_IDENT_STRING		" Allwinner Technology"
> 
> +#define CONFIG_ENV_OFFSET		(544 << 10) /* (8 + 24 + 512) KiB */
> #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
> 
> #define CONFIG_BOOTDELAY	3
> -- 
> 1.8.5.3
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot


Regards

-- Pantelis

[U-Boot] [PATCH v1 7/9] sunxi: mmc support

[Ian Campbell]

On Fri, 2014-03-14 at 17:36 +0200, Pantelis Antoniou wrote:
> [...]

Thanks for your review. It seems there are still quite a few issues
dating back to the original allwinner dumps here.

@linux-sunxi: if anyone wants to volunteer to help cleanup this
particular driver I'd be very happy -- there's a lot of it!

> +
> > +static void dumpmmcreg(struct sunxi_mmc *reg)
> > +{
> > +	debug("dump mmc registers:\n");
> > +	debug("gctrl     0x%08x\n", reg->gctrl);
> > +	debug("clkcr     0x%08x\n", reg->clkcr);
> > +	debug("timeout   0x%08x\n", reg->timeout);
> > +	debug("width     0x%08x\n", reg->width);
> > +	debug("blksz     0x%08x\n", reg->blksz);
> [...] lots more debug(foo)
> > +}
> 
> ^^^ #ifdef DEBUG here?

I can if you prefer but debug() itself effectively includes the same
ifdef so the end result is already the same.

> [...]

> > +/* support 4 mmc hosts */
> > +struct mmc mmc_dev[4];
> > +struct sunxi_mmc_host mmc_host[4];
> > +
> 
> ^ hosts & mmc structs can be allocated even for SPL now

Can be or must be?

> > +	struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
> > +	static struct sunxi_gpio *gpio_c =
> > +	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_C];
> > +	static struct sunxi_gpio *gpio_f =
> > +	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_F];
> > +#if CONFIG_MMC1_PG
> > +	static struct sunxi_gpio *gpio_g =
> > +	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_G];
> > +#endif
> > +	static struct sunxi_gpio *gpio_h =
> > +	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_H];
> > +	static struct sunxi_gpio *gpio_i =
> > +	    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_I];
> > +	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> > +
> 
> ^ Castings are ugly; rework with a temporary variable.

Ack.

The static's here are odd too and date back to the original alwinner
code dumps. I'll get rid of them too.

> [...]
> > +	case 3:
> > +		/* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
> > +		writel(0x2222 << 16, &gpio_i->cfg[0]);
> > +		writel(0x22, &gpio_i->cfg[1]);
> > +		writel(0x555 << 8, &gpio_i->pull[0]);
> > +		writel(0x555 << 8, &gpio_i->drv[0]);
> > +		break;
> > +
> > +	default:
> > +		return -1;
> > +	}
> > +
> 
> Lots of magic constants. I have no idea what's going on here.
> Use a few defines.

Right. These came from the original allwinner dumps so I was worried
that they might be undocumented magic, but actually since the are gpio
frobbing I reckon I can figure them out.

> [...]> +	cmd = (0x1 << 31) | (0x1 << 21) | (0x1 << 13);
> > +	writel(cmd, &mmchost->reg->cmd);
> > +	while ((readl(&mmchost->reg->cmd) & (0x1 << 31)) && timeout--);
> > +	if (!timeout)
> > +		return -1;
> > +
> 
> ^ Eeek! Use udelay and a time based timeout. 

Ack.

> > +	writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
> > +
> 
> ^ Same here - Not even a timeout?

No loop here though?
[...]

> > +	rval |= (0x1 << 16);
> 
> #define ?

Ack

[...]
> Ambiguous formatting. Use { }

Ack

> [...]
> > +	/* Reset controller */
> > +	writel(0x7, &mmchost->reg->gctrl);
> > +
> 
> Magic value again.

The sum total of the docs for this one are:
	 * GCTRLREG
	 * GCTRL[2]     : DMA reset
	 * GCTRL[5]     : DMA enable

But I'll see what I can do.

[...]
> > +	} else {
> > +		buff = (unsigned int *)data->src;
> > +		for (i = 0; i < (byte_cnt >> 2); i++) {
> > +			while (--timeout &&
> > +				 (readl(&mmchost->reg->status) & (0x1 << 3)));
> > +			if (timeout <= 0)
> > +				goto out;
> > +			writel(buff[i], mmchost->database);
> > +			timeout = 0xfffff;
> > +		}
> > +	}
> > +
> 
> ^ Timeouts using time values? udelay? See above.

Ack.

> [....]
> > +	writel(rval, &mmchost->reg->idie);
> > +	writel((u32) pdes, &mmchost->reg->dlba);
> > +	writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),
> > +	       &mmchost->reg->ftrglevel);
> > +
> 
> ^ #define again?

Some of these (ftrgllevel) have no docs whatsoever, but I'll do what I
can.

> [...]

> > +	timeout = 0xfffff;
> > +	do {
> > +		status = readl(&mmchost->reg->rint);
> > +		if (!timeout-- || (status & 0xbfc2)) {
> > +			error = status & 0xbfc2;
> > +			debug("cmd timeout %x\n", error);
> > +			error = TIMEOUT;
> > +			goto out;
> > +		}
> 
> ^ Again timeouts without using time values.

I'm getting the picture ;-)

> [...]
> > +int sunxi_mmc_init(int sdc_no)
> > +{
> > +	struct mmc *mmc;
> > +
> > +	memset(&mmc_dev[sdc_no], 0, sizeof(struct mmc));
> > +	memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
> > +	mmc = &mmc_dev[sdc_no];
> > +
> > +	sprintf(mmc->name, "SUNXI SD/MMC");
> > +	mmc->priv = &mmc_host[sdc_no];
> > +	mmc->send_cmd = mmc_send_cmd;
> > +	mmc->set_ios = mmc_set_ios;
> > +	mmc->init = mmc_core_init;
> > +
> > +	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
> > +	mmc->host_caps = MMC_MODE_4BIT;
> > +	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
> > +
> > +	mmc->f_min = 400000;
> > +	mmc->f_max = 52000000;
> > +
> > +	mmc_resource_init(sdc_no);
> > +	mmc_clk_io_on(sdc_no);
> > +
> > +	mmc_register(mmc);
> > +
> 
> ^ The mmc_registeration sequence has changed, but not landed at master yet.

Do you have a reference handy for this?

Thanks again, sorry this driver is such a mess (I must confess I didn't
look at it that closely when I cherry picked it).

Ian.

[U-Boot] [linux-sunxi] Re: [PATCH v1 7/9] sunxi: mmc support

[Chen-Yu Tsai]

On Mon, Mar 17, 2014 at 4:38 AM, Ian Campbell <ijc@hellion.org.uk> wrote:
> On Fri, 2014-03-14 at 17:36 +0200, Pantelis Antoniou wrote:
>> [...]
>
> Thanks for your review. It seems there are still quite a few issues
> dating back to the original allwinner dumps here.
>
> @linux-sunxi: if anyone wants to volunteer to help cleanup this
> particular driver I'd be very happy -- there's a lot of it!
>
>> +
>> > +static void dumpmmcreg(struct sunxi_mmc *reg)
>> > +{
>> > +   debug("dump mmc registers:\n");
>> > +   debug("gctrl     0x%08x\n", reg->gctrl);
>> > +   debug("clkcr     0x%08x\n", reg->clkcr);
>> > +   debug("timeout   0x%08x\n", reg->timeout);
>> > +   debug("width     0x%08x\n", reg->width);
>> > +   debug("blksz     0x%08x\n", reg->blksz);
>> [...] lots more debug(foo)
>> > +}
>>
>> ^^^ #ifdef DEBUG here?
>
> I can if you prefer but debug() itself effectively includes the same
> ifdef so the end result is already the same.
>
>> [...]
>
>> > +/* support 4 mmc hosts */
>> > +struct mmc mmc_dev[4];
>> > +struct sunxi_mmc_host mmc_host[4];
>> > +
>>
>> ^ hosts & mmc structs can be allocated even for SPL now
>
> Can be or must be?
>
>> > +   struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
>> > +   static struct sunxi_gpio *gpio_c =
>> > +       &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_C];
>> > +   static struct sunxi_gpio *gpio_f =
>> > +       &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_F];
>> > +#if CONFIG_MMC1_PG
>> > +   static struct sunxi_gpio *gpio_g =
>> > +       &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_G];
>> > +#endif
>> > +   static struct sunxi_gpio *gpio_h =
>> > +       &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_H];
>> > +   static struct sunxi_gpio *gpio_i =
>> > +       &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_I];
>> > +   struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>> > +
>>
>> ^ Castings are ugly; rework with a temporary variable.
>
> Ack.
>
> The static's here are odd too and date back to the original alwinner
> code dumps. I'll get rid of them too.

You can drop the gpio ones in favor of using the sunxi gpio driver.

>> [...]
>> > +   case 3:
>> > +           /* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
>> > +           writel(0x2222 << 16, &gpio_i->cfg[0]);
>> > +           writel(0x22, &gpio_i->cfg[1]);
>> > +           writel(0x555 << 8, &gpio_i->pull[0]);
>> > +           writel(0x555 << 8, &gpio_i->drv[0]);
>> > +           break;
>> > +
>> > +   default:
>> > +           return -1;
>> > +   }
>> > +
>>
>> Lots of magic constants. I have no idea what's going on here.
>> Use a few defines.
>
> Right. These came from the original allwinner dumps so I was worried
> that they might be undocumented magic, but actually since the are gpio
> frobbing I reckon I can figure them out.

Should be something like this:

        for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
                sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
                sunxi_gpio_set_drv(pin, 1);
                sunxi_gpio_set_pull(pin, SUNXI_PULL_UP);
        }

Note that SUNXI_GPI_* and SUNXI_PULL_* have not been defined.

I will send a patch for both the macros and MMC pinmux setting.

[..]

Thanks for working on this!


Cheers
ChenYu

[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Ian Campbell]

Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
ldscripts" vs v2014.01.

As well as the following signed-off-by the sunxi branch shows commits to these
files authored by the following:
  Henrik Nordstrom
  Tom Cubie

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
---
 Makefile                                |  15 +++
 arch/arm/cpu/armv7/sunxi/config.mk      |   8 ++
 arch/arm/cpu/armv7/sunxi/u-boot-spl.lds |  69 ++++++++++++++
 boards.cfg                              |   1 +
 include/configs/sunxi-common.h          |  45 +++++++++
 spl/Makefile                            |  12 +++
 tools/.gitignore                        |   1 +
 tools/Makefile                          |   6 ++
 tools/mksunxiboot.README                |  13 +++
 tools/mksunxiboot.c                     | 163 ++++++++++++++++++++++++++++++++
 10 files changed, 333 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/config.mk
 create mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
 create mode 100644 tools/mksunxiboot.README
 create mode 100644 tools/mksunxiboot.c

diff --git a/Makefile b/Makefile
index 47a03e3..ff1f64e 100644
--- a/Makefile
+++ b/Makefile
@@ -491,6 +491,16 @@ $(obj)u-boot.spr:	$(obj)u-boot.img $(obj)spl/u-boot-spl.bin
 			--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff $@
 		cat $(obj)u-boot.img >> $@
 
+# sunxi: Combined object with SPL U-Boot with sunxi header (sunxi-spl.bin)
+# and the full-blown U-Boot attached to it
+$(obj)u-boot-sunxi-with-spl.bin: $(obj)spl/sunxi-spl.bin $(obj)u-boot.img
+		tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \
+			of=$(obj)spl/sunxi-spl-pad.bin 2>/dev/null
+		dd if=$(obj)spl/sunxi-spl.bin of=$(obj)spl/sunxi-spl-pad.bin \
+			conv=notrunc 2>/dev/null
+		cat $(obj)spl/sunxi-spl-pad.bin $(obj)u-boot.img > $@
+		rm $(obj)spl/sunxi-spl-pad.bin
+
 ifneq ($(CONFIG_TEGRA),)
 $(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
@@ -578,6 +588,9 @@ $(obj)spl/u-boot-spl.bin:	$(SUBDIR_TOOLS) depend
 $(obj)tpl/u-boot-tpl.bin:	$(SUBDIR_TOOLS) depend
 		$(MAKE) -C spl all CONFIG_TPL_BUILD=y
 
+$(obj)spl/sunxi-spl.bin:	$(SUBDIR_TOOLS) depend
+		$(MAKE) -C spl all
+
 # Explicitly make _depend in subdirs containing multiple targets to prevent
 # parallel sub-makes creating .depend files simultaneously.
 depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE) \
@@ -799,6 +812,7 @@ clean:
 	       $(obj)tools/dump{env,}image		  \
 	       $(obj)tools/mk{env,}image   $(obj)tools/mpc86x_clk	  \
 	       $(obj)tools/mk{$(BOARD),}spl				  \
+	       $(obj)tools/mksunxiboot					  \
 	       $(obj)tools/mxsboot					  \
 	       $(obj)tools/ncb		   $(obj)tools/ubsha1		  \
 	       $(obj)tools/kernel-doc/docproc				  \
@@ -855,6 +869,7 @@ clobber:	tidy
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
 	@rm -f $(obj)dts/*.tmp
 	@rm -f $(obj)spl/u-boot-spl{,-pad}.ais
+	@rm -f $(obj)spl/sun?i-spl.bin
 
 mrproper \
 distclean:	clobber unconfig
diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk
new file mode 100644
index 0000000..9ce48b4
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/config.mk
@@ -0,0 +1,8 @@
+# Build a combined spl + u-boot image
+ifdef CONFIG_SPL
+ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_SPL_FEL
+ALL-y = $(obj)u-boot-sunxi-with-spl.bin
+endif
+endif
+endif
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
new file mode 100644
index 0000000..2a3b497
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Based on omap-common/u-boot-spl.lds:
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text)
+		*(.text*)
+	} > .sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} > .sdram
+}
diff --git a/boards.cfg b/boards.cfg
index 6c35a40..a513376 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -353,6 +353,7 @@ Active  arm         armv7          rmobile     renesas         koelsch
 Active  arm         armv7          s5pc1xx     samsung         goni                s5p_goni                             -                                                                                                                                 Mateusz Zalega <m.zalega@samsung.com>
 Active  arm         armv7          s5pc1xx     samsung         smdkc100            smdkc100                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
 Active  arm         armv7          socfpga     altera          socfpga             socfpga_cyclone5                     -                                                                                                                                 -
+Active  arm         armv7          sunxi       -               sunxi               Cubietruck                           sun7i:CUBIETRUCK,SPL                                                                                                              -
 Active  arm         armv7          sunxi       -               sunxi               Cubietruck_FEL                       sun7i:CUBIETRUCK,SPL_FEL                                                                                                          -
 Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
 Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1afdeb2..1f32304 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -34,6 +34,11 @@
  */
 #define CONFIG_ALLWINNER	/* It's a Allwinner chip */
 #define CONFIG_SUNXI		/* which is sunxi family */
+#ifdef CONFIG_SPL_BUILD
+#ifndef CONFIG_SPL_FEL
+#define CONFIG_SYS_THUMB_BUILD	/* Thumbs mode to save space in SPL */
+#endif
+#endif
 
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 
@@ -69,6 +74,9 @@
 #define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
 #define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */
 
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_SETEXPR
+
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_INITRD_TAG
@@ -90,6 +98,10 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
 
+/* Flat Device Tree (FDT/DT) support */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
+
 /*
  * Miscellaneous configurable options
  */
@@ -137,21 +149,54 @@
 
 #include <config_cmd_default.h>
 
+/* Accept zimage + raw ramdisk without mkimage headers */
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT		/* with this we can access fat bootfs */
+#define CONFIG_FAT_WRITE	/* enable write access */
+#define CONFIG_CMD_EXT2		/* with this we can access ext2 bootfs */
+#define CONFIG_CMD_EXT4		/* with this we can access ext4 bootfs */
+
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 
+#ifdef CONFIG_SPL_FEL
+
 #define CONFIG_SPL
 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds"
 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi"
 #define CONFIG_SPL_TEXT_BASE		0x2000
 #define CONFIG_SPL_MAX_SIZE		0x4000		/* 16 KiB */
+
+#else /* CONFIG_SPL */
+
+#define CONFIG_SPL_BSS_START_ADDR	0x50000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KiB */
+
+#define CONFIG_SPL_TEXT_BASE		0x20		/* sram start+header */
+#define CONFIG_SPL_MAX_SIZE		0x5fe0		/* 24KB on sun4i/sun7i */
+
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	80	/* 40KiB */
+#define CONFIG_SPL_PAD_TO		32768		/* decimal for 'dd' */
+
+#endif /* CONFIG_SPL */
+
 /* end of 32 KiB in sram */
 #define LOW_LEVEL_SRAM_STACK		0x00008000
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
+#undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
 
 #define CONFIG_CONS_INDEX              1       /* UART0 */
 
diff --git a/spl/Makefile b/spl/Makefile
index 5e5472d..436b952 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -152,6 +152,12 @@ ifdef CONFIG_SAMSUNG
 ALL-y	+= $(obj)$(BOARD)-spl.bin
 endif
 
+ifdef CONFIG_SUNXI
+ifndef CONFIG_SPL_FEL
+ALL-y	+= $(obj)sunxi-spl.bin
+endif
+endif
+
 all:	$(ALL-y)
 
 ifdef CONFIG_SAMSUNG
@@ -164,6 +170,12 @@ $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin
 	$(OBJTREE)/tools/mk$(BOARD)spl $(VAR_SIZE_PARAM) $< $@
 endif
 
+ifdef CONFIG_SUNXI
+$(obj)sunxi-spl.bin: $(obj)u-boot-spl.bin
+	$(OBJTREE)/tools/mksunxiboot \
+		$(obj)u-boot-spl.bin $(obj)sunxi-spl.bin
+endif
+
 $(obj)$(SPL_BIN).bin:	$(obj)$(SPL_BIN)
 	$(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O binary $< $@
 
diff --git a/tools/.gitignore b/tools/.gitignore
index cd2f041..2fdc9bd 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -8,6 +8,7 @@
 /mkimage
 /mpc86x_clk
 /mxsboot
+/mksunxiboot
 /ncb
 /proftool
 /relocate-rela
diff --git a/tools/Makefile b/tools/Makefile
index 328cea3..3eb46e6 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -56,6 +56,7 @@ BIN_FILES-y += mkimage$(SFX)
 BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX)
 BIN_FILES-$(CONFIG_EXYNOS5420) += mk$(BOARD)spl$(SFX)
 BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
+BIN_FILES-$(CONFIG_SUNXI) += mksunxiboot$(SFX)
 BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
 BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
 BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
@@ -97,6 +98,7 @@ OBJ_FILES-$(CONFIG_EXYNOS_SPL) += mkexynosspl.o
 OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
 OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
 OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
+OBJ_FILES-$(CONFIG_SUNXI) += mksunxiboot.o
 OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
 OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
 OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
@@ -266,6 +268,10 @@ $(obj)mpc86x_clk$(SFX):	$(obj)mpc86x_clk.o
 	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
 	$(HOSTSTRIP) $@
 
+$(obj)mksunxiboot$(SFX):	$(obj)mksunxiboot.o
+	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+	$(HOSTSTRIP) $@
+
 $(obj)mxsboot$(SFX):	$(obj)mxsboot.o
 	$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
 	$(HOSTSTRIP) $@
diff --git a/tools/mksunxiboot.README b/tools/mksunxiboot.README
new file mode 100644
index 0000000..5838778
--- /dev/null
+++ b/tools/mksunxiboot.README
@@ -0,0 +1,13 @@
+This program make a arm binary file can be loaded by Allwinner A10 and related
+chips from storage media such as nand and mmc.
+
+More information about A10 boot, please refer to
+http://rhombus-tech.net/allwinner_a10/a10_boot_process/
+
+To compile this program, just type make, you will get 'mksunxiboot'.
+
+To use it,
+$./mksunxiboot u-boot.bin u-boot-mmc.bin
+then you can write it to a mmc card with dd.
+$sudo dd if=u-boot-mmc.bin of=/dev/sdb bs=1024 seek=8
+then insert your mmc card to your A10 tablet, you can boot from mmc card.
diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c
new file mode 100644
index 0000000..bc41912
--- /dev/null
+++ b/tools/mksunxiboot.c
@@ -0,0 +1,163 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * a simple tool to generate bootable image for sunxi platform.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <fcntl.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+typedef unsigned char u8;
+typedef unsigned int u32;
+
+/* boot head definition from sun4i boot code */
+struct boot_file_head {
+	u32 jump_instruction;	/* one intruction jumping to real code */
+	u8 magic[8];		/* ="eGON.BT0" or "eGON.BT1", not C-style str */
+	u32 check_sum;		/* generated by PC */
+	u32 length;		/* generated by PC */
+#if 1
+	/* We use a simplified header, only filling in what is needed by the
+	 * boot ROM. To be compatible with Allwinner tools the larger header
+	 * below should be used, followed by a custom header if desired. */
+	u8 pad[12];		/* align to 32 bytes */
+#else
+	u32 pub_head_size;	/* the size of boot_file_head */
+	u8 pub_head_vsn[4];	/* the version of boot_file_head */
+	u8 file_head_vsn[4];	/* the version of boot0_file_head or
+				   boot1_file_head */
+	u8 Boot_vsn[4];		/* Boot version */
+	u8 eGON_vsn[4];		/* eGON version */
+	u8 platform[8];		/* platform information */
+#endif
+};
+
+#define BOOT0_MAGIC                     "eGON.BT0"
+#define STAMP_VALUE                     0x5F0A6C39
+
+/* check sum functon from sun4i boot code */
+int gen_check_sum(void *boot_buf)
+{
+	struct boot_file_head *head_p;
+	u32 length;
+	u32 *buf;
+	u32 loop;
+	u32 i;
+	u32 sum;
+
+	head_p = (struct boot_file_head *)boot_buf;
+	length = head_p->length;
+	if ((length & 0x3) != 0)	/* must 4-byte-aligned */
+		return -1;
+	buf = (u32 *)boot_buf;
+	head_p->check_sum = STAMP_VALUE;	/* fill stamp */
+	loop = length >> 2;
+
+	/* calculate the sum */
+	for (i = 0, sum = 0; i < loop; i++)
+		sum += buf[i];
+
+	/* write back check sum */
+	head_p->check_sum = sum;
+
+	return 0;
+}
+
+#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1)
+#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
+
+#define SUN4I_SRAM_SIZE 0x7600	/* 0x7748+ is used by BROM */
+#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head))
+#define BLOCK_SIZE 512
+
+struct boot_img {
+	struct boot_file_head header;
+	char code[SRAM_LOAD_MAX_SIZE];
+	char pad[BLOCK_SIZE];
+};
+
+int main(int argc, char *argv[])
+{
+	int fd_in, fd_out;
+	struct boot_img img;
+	unsigned file_size, load_size;
+	int count;
+
+	if (argc < 2) {
+		printf("\tThis program makes an input bin file to sun4i " \
+		       "bootable image.\n" \
+		       "\tUsage: %s input_file out_putfile\n", argv[0]);
+		return EXIT_FAILURE;
+	}
+
+	fd_in = open(argv[1], O_RDONLY);
+	if (fd_in < 0) {
+		perror("Open input file:");
+		return EXIT_FAILURE;
+	}
+
+	memset((void *)img.pad, 0, BLOCK_SIZE);
+
+	/* get input file size */
+	file_size = lseek(fd_in, 0, SEEK_END);
+	printf("File size: 0x%x\n", file_size);
+
+	if (file_size > SRAM_LOAD_MAX_SIZE) {
+		fprintf(stderr, "ERROR: File too large!\n");
+		return EXIT_FAILURE;
+	} else
+		load_size = ALIGN(file_size, sizeof(int));
+	printf("Load size: 0x%x\n", load_size);
+
+	fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666);
+	if (fd_out < 0) {
+		perror("Open output file:");
+		return EXIT_FAILURE;
+	}
+
+	/* read file to buffer to calculate checksum */
+	lseek(fd_in, 0, SEEK_SET);
+	count = read(fd_in, img.code, load_size);
+	printf("Read 0x%x bytes\n", count);
+
+	/* fill the header */
+	img.header.jump_instruction =	/* b instruction */
+		0xEA000000 |	/* jump to the first instr after the header */
+		((sizeof(struct boot_file_head) / sizeof(int) - 2)
+		 & 0x00FFFFFF);
+	memcpy(img.header.magic, BOOT0_MAGIC, 8);	/* no '0' termination */
+	img.header.length =
+		ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE);
+	gen_check_sum((void *)&img);
+
+	count = write(fd_out, (void *)&img, img.header.length);
+	printf("Write 0x%x bytes\n", count);
+
+	close(fd_in);
+	close(fd_out);
+
+	return EXIT_SUCCESS;
+}
-- 
1.8.5.3

[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:

> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> ldscripts" vs v2014.01.
[snip]
> +/* Flat Device Tree (FDT/DT) support */
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)

This seems pretty small.  This is to keep things from being relocated
into highmem right?

-- 
Tom
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[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Hans de Goede]

Hi,

On 03/14/2014 03:17 PM, Tom Rini wrote:
> On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:
> 
>> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
>> ldscripts" vs v2014.01.
> [snip]
>> +/* Flat Device Tree (FDT/DT) support */
>> +#define CONFIG_OF_LIBFDT
>> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
> 
> This seems pretty small.  This is to keep things from being relocated
> into highmem right?

Hmm, this reminds me that we currently need to do a "env set fdt_high ffffffff"
in our boot scripts to get ftd to work at all. Would be nice to fix this for
upstream. I'm afraid I'm clueless as to why we (sunxi) need it, but we do.

Regards,

Hans

[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Tom Rini]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 03/14/2014 02:50 PM, Hans de Goede wrote:
> Hi,
> 
> On 03/14/2014 03:17 PM, Tom Rini wrote:
>> On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:
>>
>>> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
>>> ldscripts" vs v2014.01.
>> [snip]
>>> +/* Flat Device Tree (FDT/DT) support */
>>> +#define CONFIG_OF_LIBFDT
>>> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
>>
>> This seems pretty small.  This is to keep things from being relocated
>> into highmem right?
> 
> Hmm, this reminds me that we currently need to do a "env set fdt_high ffffffff"
> in our boot scripts to get ftd to work at all. Would be nice to fix this for
> upstream. I'm afraid I'm clueless as to why we (sunxi) need it, but we do.

You want to be setting bootm_low (even for bootz, it's about the
underlying boot mechanics that bootz and bootelf and ... hook into) to
the amount of lowmem the kernel will have.  We do this because we do
want to make sure that the device tree isn't overwritten by the kernel
BSS or similar.  Everyone with more DDR than kernel lowmem needs to be
doing something along these lines.

- -- 
Tom
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[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Ian Campbell]

On Fri, 2014-03-14 at 15:03 -0400, Tom Rini wrote:
> On 03/14/2014 02:50 PM, Hans de Goede wrote:
> > Hi,
> > 
> > On 03/14/2014 03:17 PM, Tom Rini wrote:
> >> On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:
> >>
> >>> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> >>> ldscripts" vs v2014.01.
> >> [snip]
> >>> +/* Flat Device Tree (FDT/DT) support */
> >>> +#define CONFIG_OF_LIBFDT
> >>> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
> >>
> >> This seems pretty small.  This is to keep things from being relocated
> >> into highmem right?
> > 
> > Hmm, this reminds me that we currently need to do a "env set fdt_high ffffffff"
> > in our boot scripts to get ftd to work at all. Would be nice to fix this for
> > upstream. I'm afraid I'm clueless as to why we (sunxi) need it, but we do.
> 
> You want to be setting bootm_low (even for bootz, it's about the
> underlying boot mechanics that bootz and bootelf and ... hook into) to
> the amount of lowmem the kernel will have.  We do this because we do
> want to make sure that the device tree isn't overwritten by the kernel
> BSS or similar.  Everyone with more DDR than kernel lowmem needs to be
> doing something along these lines.

So, I'm confused about what to do here ;-)

AFAICS none of the existing platforms in u-boot.git are setting
bootm_low in their default environment.

README suggests that bootm_low is the lowest address allowed for use by
bootm/z rather than the limit, from the docs it seems that
CONFIG_SYS_BOOTMAPSZ (overridden by env bootm_mapsize) is the limit

bootm_low defaults to CONFIG_SYS_SDRAM_BASE, which sunxi sets, and this
seems logical to me since kernel's lowmem mapping starts at offset 0
into RAM.

I think we probably do want to set BOOTMAPSZ to something like 256MB,
which seems to be the highest in tree (although the vast majority use
8MB...). But I'm not sure that explains why fdt_high is needed today.
I'll have a play.

Ian.

[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Ian Campbell]

On Sun, 2014-03-16 at 15:19 +0000, Ian Campbell wrote:
> On Fri, 2014-03-14 at 15:03 -0400, Tom Rini wrote:
> > On 03/14/2014 02:50 PM, Hans de Goede wrote:
> > > Hi,
> > > 
> > > On 03/14/2014 03:17 PM, Tom Rini wrote:
> > >> On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:
> > >>
> > >>> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> > >>> ldscripts" vs v2014.01.
> > >> [snip]
> > >>> +/* Flat Device Tree (FDT/DT) support */
> > >>> +#define CONFIG_OF_LIBFDT
> > >>> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
> > >>
> > >> This seems pretty small.  This is to keep things from being relocated
> > >> into highmem right?
> > > 
> > > Hmm, this reminds me that we currently need to do a "env set fdt_high ffffffff"
> > > in our boot scripts to get ftd to work at all. Would be nice to fix this for
> > > upstream. I'm afraid I'm clueless as to why we (sunxi) need it, but we do.
> > 
> > You want to be setting bootm_low (even for bootz, it's about the
> > underlying boot mechanics that bootz and bootelf and ... hook into) to
> > the amount of lowmem the kernel will have.  We do this because we do
> > want to make sure that the device tree isn't overwritten by the kernel
> > BSS or similar.  Everyone with more DDR than kernel lowmem needs to be
> > doing something along these lines.
> 
> So, I'm confused about what to do here ;-)
> 
> AFAICS none of the existing platforms in u-boot.git are setting
> bootm_low in their default environment.
> 
> README suggests that bootm_low is the lowest address allowed for use by
> bootm/z rather than the limit, from the docs it seems that
> CONFIG_SYS_BOOTMAPSZ (overridden by env bootm_mapsize) is the limit
> 
> bootm_low defaults to CONFIG_SYS_SDRAM_BASE, which sunxi sets, and this
> seems logical to me since kernel's lowmem mapping starts at offset 0
> into RAM.
> 
> I think we probably do want to set BOOTMAPSZ to something like 256MB,
> which seems to be the highest in tree (although the vast majority use
> 8MB...). But I'm not sure that explains why fdt_high is needed today.
> I'll have a play.

So setting BOOTMAPSZ to e.g. 256MB limits the fdt load address as you
would expect.

But it seems to not make any difference for the initramfs which still
gets loaded to the top of RAM. This is consistent with README which says
that unless initrd_high is set the ramdisk will be loaded as high as
possible, without reference to BOOTMAPSZ. Supposedly setting initrd_high
to "no", "off" or "0" should cause initrd relocation to obey BOOTMAPSZ
-- but at least in my experiments it does not seem to do so.

boot_ramdisk_high() doesn't seem to make any reference to
bootm_{low,size,etc} like I would expect and with initrd_high==0 it
calls lmb_alloc which allocates anywhere. This is in contrast with
boot_relocate_fdt which uses getenv_bootm_mapsize() and
getenv_bootm_low().

It looks to me like the initrd reloc logic is wrong -- but it's been
that way for such a long time I think I must be mistaken.

Ian.

[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Tom Rini]

On Sun, Mar 16, 2014 at 04:45:57PM +0000, Ian Campbell wrote:
> On Sun, 2014-03-16 at 15:19 +0000, Ian Campbell wrote:
> > On Fri, 2014-03-14 at 15:03 -0400, Tom Rini wrote:
> > > On 03/14/2014 02:50 PM, Hans de Goede wrote:
> > > > Hi,
> > > > 
> > > > On 03/14/2014 03:17 PM, Tom Rini wrote:
> > > >> On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:
> > > >>
> > > >>> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> > > >>> ldscripts" vs v2014.01.
> > > >> [snip]
> > > >>> +/* Flat Device Tree (FDT/DT) support */
> > > >>> +#define CONFIG_OF_LIBFDT
> > > >>> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
> > > >>
> > > >> This seems pretty small.  This is to keep things from being relocated
> > > >> into highmem right?
> > > > 
> > > > Hmm, this reminds me that we currently need to do a "env set fdt_high ffffffff"
> > > > in our boot scripts to get ftd to work at all. Would be nice to fix this for
> > > > upstream. I'm afraid I'm clueless as to why we (sunxi) need it, but we do.
> > > 
> > > You want to be setting bootm_low (even for bootz, it's about the
> > > underlying boot mechanics that bootz and bootelf and ... hook into) to
> > > the amount of lowmem the kernel will have.  We do this because we do
> > > want to make sure that the device tree isn't overwritten by the kernel
> > > BSS or similar.  Everyone with more DDR than kernel lowmem needs to be
> > > doing something along these lines.
> > 
> > So, I'm confused about what to do here ;-)
> > 
> > AFAICS none of the existing platforms in u-boot.git are setting
> > bootm_low in their default environment.

Yes.  http://patchwork.ozlabs.org/patch/329210/ gets things right for
some subset of TI platforms and I'll be picking that up soon.  Or maybe
a v2.

> > README suggests that bootm_low is the lowest address allowed for use by
> > bootm/z rather than the limit, from the docs it seems that
> > CONFIG_SYS_BOOTMAPSZ (overridden by env bootm_mapsize) is the limit
> > 
> > bootm_low defaults to CONFIG_SYS_SDRAM_BASE, which sunxi sets, and this
> > seems logical to me since kernel's lowmem mapping starts at offset 0
> > into RAM.
> > 
> > I think we probably do want to set BOOTMAPSZ to something like 256MB,
> > which seems to be the highest in tree (although the vast majority use
> > 8MB...). But I'm not sure that explains why fdt_high is needed today.
> > I'll have a play.
> 
> So setting BOOTMAPSZ to e.g. 256MB limits the fdt load address as you
> would expect.
> 
> But it seems to not make any difference for the initramfs which still
> gets loaded to the top of RAM. This is consistent with README which says
> that unless initrd_high is set the ramdisk will be loaded as high as
> possible, without reference to BOOTMAPSZ. Supposedly setting initrd_high
> to "no", "off" or "0" should cause initrd relocation to obey BOOTMAPSZ
> -- but at least in my experiments it does not seem to do so.
> 
> boot_ramdisk_high() doesn't seem to make any reference to
> bootm_{low,size,etc} like I would expect and with initrd_high==0 it
> calls lmb_alloc which allocates anywhere. This is in contrast with
> boot_relocate_fdt which uses getenv_bootm_mapsize() and
> getenv_bootm_low().
> 
> It looks to me like the initrd reloc logic is wrong -- but it's been
> that way for such a long time I think I must be mistaken.

I think after reading what you're saying, things are very unclear,
unfortunately.  What you can do, but is very odd after thinking about it
is if you set bootm_low only and not any of the size things, it works as
a constraint on the upper bounds so initrd nor fdt are put above that.
But that's really seeming like a side effect rather than an intent.  I'm
going to whack at this more..

-- 
Tom
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[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Ian Campbell]

On Mon, 2014-03-17 at 11:20 -0400, Tom Rini wrote:
> On Sun, Mar 16, 2014 at 04:45:57PM +0000, Ian Campbell wrote:
> > On Sun, 2014-03-16 at 15:19 +0000, Ian Campbell wrote:
> > > On Fri, 2014-03-14 at 15:03 -0400, Tom Rini wrote:
> > > > On 03/14/2014 02:50 PM, Hans de Goede wrote:
> > > > > Hi,
> > > > > 
> > > > > On 03/14/2014 03:17 PM, Tom Rini wrote:
> > > > >> On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:
> > > > >>
> > > > >>> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> > > > >>> ldscripts" vs v2014.01.
> > > > >> [snip]
> > > > >>> +/* Flat Device Tree (FDT/DT) support */
> > > > >>> +#define CONFIG_OF_LIBFDT
> > > > >>> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
> > > > >>
> > > > >> This seems pretty small.  This is to keep things from being relocated
> > > > >> into highmem right?
> > > > > 
> > > > > Hmm, this reminds me that we currently need to do a "env set fdt_high ffffffff"
> > > > > in our boot scripts to get ftd to work at all. Would be nice to fix this for
> > > > > upstream. I'm afraid I'm clueless as to why we (sunxi) need it, but we do.
> > > > 
> > > > You want to be setting bootm_low (even for bootz, it's about the
> > > > underlying boot mechanics that bootz and bootelf and ... hook into) to
> > > > the amount of lowmem the kernel will have.  We do this because we do
> > > > want to make sure that the device tree isn't overwritten by the kernel
> > > > BSS or similar.  Everyone with more DDR than kernel lowmem needs to be
> > > > doing something along these lines.
> > > 
> > > So, I'm confused about what to do here ;-)
> > > 
> > > AFAICS none of the existing platforms in u-boot.git are setting
> > > bootm_low in their default environment.
> 
> Yes.  http://patchwork.ozlabs.org/patch/329210/ gets things right for
> some subset of TI platforms and I'll be picking that up soon.  Or maybe
> a v2.

You are dropping fdt_high=0xffffffff here, is that deliberate?

I suppose this is offset by the addition of bootm_size which keeps
things working? (or does it, I'm very confused now...)

> > > README suggests that bootm_low is the lowest address allowed for use by
> > > bootm/z rather than the limit, from the docs it seems that
> > > CONFIG_SYS_BOOTMAPSZ (overridden by env bootm_mapsize) is the limit
> > > 
> > > bootm_low defaults to CONFIG_SYS_SDRAM_BASE, which sunxi sets, and this
> > > seems logical to me since kernel's lowmem mapping starts at offset 0
> > > into RAM.
> > > 
> > > I think we probably do want to set BOOTMAPSZ to something like 256MB,
> > > which seems to be the highest in tree (although the vast majority use
> > > 8MB...). But I'm not sure that explains why fdt_high is needed today.
> > > I'll have a play.
> > 
> > So setting BOOTMAPSZ to e.g. 256MB limits the fdt load address as you
> > would expect.
> > 
> > But it seems to not make any difference for the initramfs which still
> > gets loaded to the top of RAM. This is consistent with README which says
> > that unless initrd_high is set the ramdisk will be loaded as high as
> > possible, without reference to BOOTMAPSZ. Supposedly setting initrd_high
> > to "no", "off" or "0" should cause initrd relocation to obey BOOTMAPSZ
> > -- but at least in my experiments it does not seem to do so.
> > 
> > boot_ramdisk_high() doesn't seem to make any reference to
> > bootm_{low,size,etc} like I would expect and with initrd_high==0 it
> > calls lmb_alloc which allocates anywhere. This is in contrast with
> > boot_relocate_fdt which uses getenv_bootm_mapsize() and
> > getenv_bootm_low().
> > 
> > It looks to me like the initrd reloc logic is wrong -- but it's been
> > that way for such a long time I think I must be mistaken.
> 
> I think after reading what you're saying, things are very unclear,
> unfortunately.

I'm glad it's not just me!

>   What you can do, but is very odd after thinking about it
> is if you set bootm_low only and not any of the size things, it works as
> a constraint on the upper bounds so initrd nor fdt are put above that.
> But that's really seeming like a side effect rather than an intent.

Right, I don't think I want to add any weirdness, unless all the cool
kids are going to be doing it of course ;-)

> I'm going to whack at this more..

Thanks. I think for now with this series I can just set BOOTMAPSZ to
256MB without making this problem any better or worse and we can fixup
things later in whatever is determined to be the right solution. Is that
OK with you?

Ian.

[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Tom Rini]

On Mon, Mar 17, 2014 at 03:29:44PM +0000, Ian Campbell wrote:
> On Mon, 2014-03-17 at 11:20 -0400, Tom Rini wrote:
> > On Sun, Mar 16, 2014 at 04:45:57PM +0000, Ian Campbell wrote:
> > > On Sun, 2014-03-16 at 15:19 +0000, Ian Campbell wrote:
> > > > On Fri, 2014-03-14 at 15:03 -0400, Tom Rini wrote:
> > > > > On 03/14/2014 02:50 PM, Hans de Goede wrote:
> > > > > > Hi,
> > > > > > 
> > > > > > On 03/14/2014 03:17 PM, Tom Rini wrote:
> > > > > >> On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:
> > > > > >>
> > > > > >>> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> > > > > >>> ldscripts" vs v2014.01.
> > > > > >> [snip]
> > > > > >>> +/* Flat Device Tree (FDT/DT) support */
> > > > > >>> +#define CONFIG_OF_LIBFDT
> > > > > >>> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
> > > > > >>
> > > > > >> This seems pretty small.  This is to keep things from being relocated
> > > > > >> into highmem right?
> > > > > > 
> > > > > > Hmm, this reminds me that we currently need to do a "env set fdt_high ffffffff"
> > > > > > in our boot scripts to get ftd to work at all. Would be nice to fix this for
> > > > > > upstream. I'm afraid I'm clueless as to why we (sunxi) need it, but we do.
> > > > > 
> > > > > You want to be setting bootm_low (even for bootz, it's about the
> > > > > underlying boot mechanics that bootz and bootelf and ... hook into) to
> > > > > the amount of lowmem the kernel will have.  We do this because we do
> > > > > want to make sure that the device tree isn't overwritten by the kernel
> > > > > BSS or similar.  Everyone with more DDR than kernel lowmem needs to be
> > > > > doing something along these lines.
> > > > 
> > > > So, I'm confused about what to do here ;-)
> > > > 
> > > > AFAICS none of the existing platforms in u-boot.git are setting
> > > > bootm_low in their default environment.
> > 
> > Yes.  http://patchwork.ozlabs.org/patch/329210/ gets things right for
> > some subset of TI platforms and I'll be picking that up soon.  Or maybe
> > a v2.
> 
> You are dropping fdt_high=0xffffffff here, is that deliberate?
> 
> I suppose this is offset by the addition of bootm_size which keeps
> things working? (or does it, I'm very confused now...)

Intentional and confusing.

> > > > README suggests that bootm_low is the lowest address allowed for use by
> > > > bootm/z rather than the limit, from the docs it seems that
> > > > CONFIG_SYS_BOOTMAPSZ (overridden by env bootm_mapsize) is the limit
> > > > 
> > > > bootm_low defaults to CONFIG_SYS_SDRAM_BASE, which sunxi sets, and this
> > > > seems logical to me since kernel's lowmem mapping starts at offset 0
> > > > into RAM.
> > > > 
> > > > I think we probably do want to set BOOTMAPSZ to something like 256MB,
> > > > which seems to be the highest in tree (although the vast majority use
> > > > 8MB...). But I'm not sure that explains why fdt_high is needed today.
> > > > I'll have a play.
> > > 
> > > So setting BOOTMAPSZ to e.g. 256MB limits the fdt load address as you
> > > would expect.
> > > 
> > > But it seems to not make any difference for the initramfs which still
> > > gets loaded to the top of RAM. This is consistent with README which says
> > > that unless initrd_high is set the ramdisk will be loaded as high as
> > > possible, without reference to BOOTMAPSZ. Supposedly setting initrd_high
> > > to "no", "off" or "0" should cause initrd relocation to obey BOOTMAPSZ
> > > -- but at least in my experiments it does not seem to do so.
> > > 
> > > boot_ramdisk_high() doesn't seem to make any reference to
> > > bootm_{low,size,etc} like I would expect and with initrd_high==0 it
> > > calls lmb_alloc which allocates anywhere. This is in contrast with
> > > boot_relocate_fdt which uses getenv_bootm_mapsize() and
> > > getenv_bootm_low().
> > > 
> > > It looks to me like the initrd reloc logic is wrong -- but it's been
> > > that way for such a long time I think I must be mistaken.
> > 
> > I think after reading what you're saying, things are very unclear,
> > unfortunately.
> 
> I'm glad it's not just me!
> 
> >   What you can do, but is very odd after thinking about it
> > is if you set bootm_low only and not any of the size things, it works as
> > a constraint on the upper bounds so initrd nor fdt are put above that.
> > But that's really seeming like a side effect rather than an intent.
> 
> Right, I don't think I want to add any weirdness, unless all the cool
> kids are going to be doing it of course ;-)
> 
> > I'm going to whack at this more..
> 
> Thanks. I think for now with this series I can just set BOOTMAPSZ to
> 256MB without making this problem any better or worse and we can fixup
> things later in whatever is determined to be the right solution. Is that
> OK with you?

Yes, you can do that for now and I'll bounce ideas off you in v2 of the
TI series at least..

-- 
Tom
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[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Tom Rini]

On Sun, Mar 16, 2014 at 03:19:40PM +0000, Ian Campbell wrote:
> On Fri, 2014-03-14 at 15:03 -0400, Tom Rini wrote:
> > On 03/14/2014 02:50 PM, Hans de Goede wrote:
> > > Hi,
> > > 
> > > On 03/14/2014 03:17 PM, Tom Rini wrote:
> > >> On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:
> > >>
> > >>> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> > >>> ldscripts" vs v2014.01.
> > >> [snip]
> > >>> +/* Flat Device Tree (FDT/DT) support */
> > >>> +#define CONFIG_OF_LIBFDT
> > >>> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
> > >>
> > >> This seems pretty small.  This is to keep things from being relocated
> > >> into highmem right?
> > > 
> > > Hmm, this reminds me that we currently need to do a "env set fdt_high ffffffff"
> > > in our boot scripts to get ftd to work at all. Would be nice to fix this for
> > > upstream. I'm afraid I'm clueless as to why we (sunxi) need it, but we do.
> > 
> > You want to be setting bootm_low (even for bootz, it's about the
> > underlying boot mechanics that bootz and bootelf and ... hook into) to
> > the amount of lowmem the kernel will have.  We do this because we do
> > want to make sure that the device tree isn't overwritten by the kernel
> > BSS or similar.  Everyone with more DDR than kernel lowmem needs to be
> > doing something along these lines.
> 
> So, I'm confused about what to do here ;-)

And I've not made things clearer with a mis-recollection of things.  I
don't know why I keep saying "bootm_low" when I mean "bootm_size" like
I've done in later patches (and thankfully, when poking people on G+).

There's three ways to say "Please ensure that the FDT and if passed initrd
do not relocate above a certain location".
1) In the environment, set bootm_size to kernel lowmem.  This means that
boot_start_lmb restricts the pool used by both fdt and initrd to that
value at the top.
2) In the environment, set fdt_high (and if using initrd, initrd_high)
to the top of lowmem.  This means that we'll make sure they don't get
relocated above that value.
3) In the environment set initrd_high to top of lowmem and set
bootm_mapsize to lowmem.

In all of the above, lowmem can be replaced with any valid size that's
also smaller than lowmem, such as 256MB.  Another option, in the
environment, is to set initrd_high and fdt_high to 0xffffffff and then
relocation is disabled.  I would _not_ recommend this in the general
case as one of the points of relocation is to ensure we don't get
overwritten by the kernel BSS.

-- 
Tom
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[U-Boot] [linux-sunxi] Re: [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Maxime Ripard]

On Mon, Mar 17, 2014 at 03:33:19PM -0400, Tom Rini wrote:
> On Sun, Mar 16, 2014 at 03:19:40PM +0000, Ian Campbell wrote:
> > On Fri, 2014-03-14 at 15:03 -0400, Tom Rini wrote:
> > > On 03/14/2014 02:50 PM, Hans de Goede wrote:
> > > > Hi,
> > > > 
> > > > On 03/14/2014 03:17 PM, Tom Rini wrote:
> > > >> On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:
> > > >>
> > > >>> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> > > >>> ldscripts" vs v2014.01.
> > > >> [snip]
> > > >>> +/* Flat Device Tree (FDT/DT) support */
> > > >>> +#define CONFIG_OF_LIBFDT
> > > >>> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
> > > >>
> > > >> This seems pretty small.  This is to keep things from being relocated
> > > >> into highmem right?
> > > > 
> > > > Hmm, this reminds me that we currently need to do a "env set fdt_high ffffffff"
> > > > in our boot scripts to get ftd to work at all. Would be nice to fix this for
> > > > upstream. I'm afraid I'm clueless as to why we (sunxi) need it, but we do.
> > > 
> > > You want to be setting bootm_low (even for bootz, it's about the
> > > underlying boot mechanics that bootz and bootelf and ... hook into) to
> > > the amount of lowmem the kernel will have.  We do this because we do
> > > want to make sure that the device tree isn't overwritten by the kernel
> > > BSS or similar.  Everyone with more DDR than kernel lowmem needs to be
> > > doing something along these lines.
> > 
> > So, I'm confused about what to do here ;-)
> 
> And I've not made things clearer with a mis-recollection of things.  I
> don't know why I keep saying "bootm_low" when I mean "bootm_size" like
> I've done in later patches (and thankfully, when poking people on G+).
> 
> There's three ways to say "Please ensure that the FDT and if passed initrd
> do not relocate above a certain location".
> 1) In the environment, set bootm_size to kernel lowmem.  This means that
> boot_start_lmb restricts the pool used by both fdt and initrd to that
> value at the top.
> 2) In the environment, set fdt_high (and if using initrd, initrd_high)
> to the top of lowmem.  This means that we'll make sure they don't get
> relocated above that value.
> 3) In the environment set initrd_high to top of lowmem and set
> bootm_mapsize to lowmem.
> 
> In all of the above, lowmem can be replaced with any valid size that's
> also smaller than lowmem, such as 256MB.  Another option, in the
> environment, is to set initrd_high and fdt_high to 0xffffffff and then
> relocation is disabled.  I would _not_ recommend this in the general
> case as one of the points of relocation is to ensure we don't get
> overwritten by the kernel BSS.

IIRC, we added it not to make sure that it was in lowmem, but because
we had issues with large enough kernels (multi_v7_defconfig + embedded
initramfs) that would overwrite the relocated DTB whenever it was
decompressing itself.

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[U-Boot] [linux-sunxi] Re: [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Tom Rini]

On Tue, Mar 18, 2014 at 09:22:50AM +0100, Maxime Ripard wrote:
> On Mon, Mar 17, 2014 at 03:33:19PM -0400, Tom Rini wrote:
> > On Sun, Mar 16, 2014 at 03:19:40PM +0000, Ian Campbell wrote:
> > > On Fri, 2014-03-14 at 15:03 -0400, Tom Rini wrote:
> > > > On 03/14/2014 02:50 PM, Hans de Goede wrote:
> > > > > Hi,
> > > > > 
> > > > > On 03/14/2014 03:17 PM, Tom Rini wrote:
> > > > >> On Fri, Mar 14, 2014 at 10:33:50AM +0000, Ian Campbell wrote:
> > > > >>
> > > > >>> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> > > > >>> ldscripts" vs v2014.01.
> > > > >> [snip]
> > > > >>> +/* Flat Device Tree (FDT/DT) support */
> > > > >>> +#define CONFIG_OF_LIBFDT
> > > > >>> +#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
> > > > >>
> > > > >> This seems pretty small.  This is to keep things from being relocated
> > > > >> into highmem right?
> > > > > 
> > > > > Hmm, this reminds me that we currently need to do a "env set fdt_high ffffffff"
> > > > > in our boot scripts to get ftd to work at all. Would be nice to fix this for
> > > > > upstream. I'm afraid I'm clueless as to why we (sunxi) need it, but we do.
> > > > 
> > > > You want to be setting bootm_low (even for bootz, it's about the
> > > > underlying boot mechanics that bootz and bootelf and ... hook into) to
> > > > the amount of lowmem the kernel will have.  We do this because we do
> > > > want to make sure that the device tree isn't overwritten by the kernel
> > > > BSS or similar.  Everyone with more DDR than kernel lowmem needs to be
> > > > doing something along these lines.
> > > 
> > > So, I'm confused about what to do here ;-)
> > 
> > And I've not made things clearer with a mis-recollection of things.  I
> > don't know why I keep saying "bootm_low" when I mean "bootm_size" like
> > I've done in later patches (and thankfully, when poking people on G+).
> > 
> > There's three ways to say "Please ensure that the FDT and if passed initrd
> > do not relocate above a certain location".
> > 1) In the environment, set bootm_size to kernel lowmem.  This means that
> > boot_start_lmb restricts the pool used by both fdt and initrd to that
> > value at the top.
> > 2) In the environment, set fdt_high (and if using initrd, initrd_high)
> > to the top of lowmem.  This means that we'll make sure they don't get
> > relocated above that value.
> > 3) In the environment set initrd_high to top of lowmem and set
> > bootm_mapsize to lowmem.
> > 
> > In all of the above, lowmem can be replaced with any valid size that's
> > also smaller than lowmem, such as 256MB.  Another option, in the
> > environment, is to set initrd_high and fdt_high to 0xffffffff and then
> > relocation is disabled.  I would _not_ recommend this in the general
> > case as one of the points of relocation is to ensure we don't get
> > overwritten by the kernel BSS.
> 
> IIRC, we added it not to make sure that it was in lowmem, but because
> we had issues with large enough kernels (multi_v7_defconfig + embedded
> initramfs) that would overwrite the relocated DTB whenever it was
> decompressing itself.

Right.  The series of problems often goes:
1) Oops, DTB moved into high mem, set fdt_high 0xffffffff to stop that
2) Oops, DTB overwritten by kernel, change fdt load addr.

Which is why relocation is a good thing (at least on the device tree
which tends to be small enough to not be a noticable thing) in the
default case.

-- 
Tom
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[U-Boot] [PATCH v1 8/9] sunxi: non-FEL SPL boot support for sun7i

[Ian Campbell]

On Mon, 2014-03-17 at 15:33 -0400, Tom Rini wrote:
> > So, I'm confused about what to do here ;-)
> 
> And I've not made things clearer with a mis-recollection of things.  I
> don't know why I keep saying "bootm_low" when I mean "bootm_size" like
> I've done in later patches (and thankfully, when poking people on G+).

Ah, making that substitution makes things make a lot more sense!

> There's three ways to say "Please ensure that the FDT and if passed initrd
> do not relocate above a certain location".
> 1) In the environment, set bootm_size to kernel lowmem.  This means that
> boot_start_lmb restricts the pool used by both fdt and initrd to that
> value at the top.
> 2) In the environment, set fdt_high (and if using initrd, initrd_high)
> to the top of lowmem.  This means that we'll make sure they don't get
> relocated above that value.
> 3) In the environment set initrd_high to top of lowmem and set
> bootm_mapsize to lowmem.

Looking at http://patchwork.ozlabs.org/patch/329210/ it seems that you
went for #1 on TI stuff -- so I am going to follow suite.

> In all of the above, lowmem can be replaced with any valid size that's
> also smaller than lowmem, such as 256MB.

256MB sounds like a good value to be starting with.

>   Another option, in the
> environment, is to set initrd_high and fdt_high to 0xffffffff and then
> relocation is disabled.  I would _not_ recommend this in the general
> case as one of the points of relocation is to ensure we don't get
> overwritten by the kernel BSS.

Sure.

Thanks,
Ian.

[U-Boot] [PATCH v1 9/9] sunxi: add gmac Ethernet support

[Ian Campbell]

Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
ldscripts" vs v2014.01.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/sunxi/board.c | 15 +++++++++
 boards.cfg                       |  4 +--
 drivers/net/Makefile             |  1 +
 drivers/net/sunxi_gmac.c         | 34 ++++++++++++++++++++
 include/configs/sunxi-common.h   | 68 ++++++++++++++++++++++++++++++++++++++++
 5 files changed, 120 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/sunxi_gmac.c

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 98cad43..73b4cf0 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -27,6 +27,8 @@
  */
 
 #include <common.h>
+#include <netdev.h>
+#include <miiphy.h>
 #include <serial.h>
 #ifdef CONFIG_SPL_BUILD
 #include <spl.h>
@@ -102,3 +104,16 @@ void enable_caches(void)
 	dcache_enable();
 }
 #endif
+
+#if defined(CONFIG_SUNXI_GMAC)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+	sunxi_gmac_initialize(bis);
+
+	return 0;
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index a513376..090e956 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -353,8 +353,8 @@ Active  arm         armv7          rmobile     renesas         koelsch
 Active  arm         armv7          s5pc1xx     samsung         goni                s5p_goni                             -                                                                                                                                 Mateusz Zalega <m.zalega@samsung.com>
 Active  arm         armv7          s5pc1xx     samsung         smdkc100            smdkc100                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
 Active  arm         armv7          socfpga     altera          socfpga             socfpga_cyclone5                     -                                                                                                                                 -
-Active  arm         armv7          sunxi       -               sunxi               Cubietruck                           sun7i:CUBIETRUCK,SPL                                                                                                              -
-Active  arm         armv7          sunxi       -               sunxi               Cubietruck_FEL                       sun7i:CUBIETRUCK,SPL_FEL                                                                                                          -
+Active  arm         armv7          sunxi       -               sunxi               Cubietruck                           sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII                                                                                             -
+Active  arm         armv7          sunxi       -               sunxi               Cubietruck_FEL                       sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII                                                                                         -
 Active  arm         armv7          u8500       st-ericsson     snowball            snowball                             -                                                                                                                                 Mathieu Poirier <mathieu.poirier@linaro.org>
 Active  arm         armv7          u8500       st-ericsson     u8500               u8500_href                           -                                                                                                                                 -
 Active  arm         armv7          vf610       freescale       vf610twr            vf610twr                             vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg                                                                         Alison Wang <b18965@freescale.com>
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 7f9ce90..2300c00 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_SH_ETHER) += sh_eth.o
 obj-$(CONFIG_SMC91111) += smc91111.o
 obj-$(CONFIG_SMC911X) += smc911x.o
 obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
+obj-$(CONFIG_SUNXI_GMAC) += sunxi_gmac.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
 obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
diff --git a/drivers/net/sunxi_gmac.c b/drivers/net/sunxi_gmac.c
new file mode 100644
index 0000000..432d7b2
--- /dev/null
+++ b/drivers/net/sunxi_gmac.c
@@ -0,0 +1,34 @@
+#include <common.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+
+int sunxi_gmac_initialize(bd_t *bis)
+{
+	int pin;
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* Set up clock gating */
+	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
+
+	/* Set MII clock */
+	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+		CCM_GMAC_CTRL_GPIT_RGMII);
+
+	/* Configure pin mux settings for GMAC */
+	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+		/* skip unused pins in RGMII mode */
+		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
+		    continue;
+		sunxi_gpio_set_cfgpin(pin, 5);
+		sunxi_gpio_set_drv(pin, 3);
+	}
+
+	designware_initialize(0, SUNXI_GMAC_BASE, 0x1, PHY_INTERFACE_MODE_RGMII);
+
+	return 0;
+}
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 1f32304..95a14f2 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -200,6 +200,74 @@
 
 #define CONFIG_CONS_INDEX              1       /* UART0 */
 
+#ifdef CONFIG_SUNXI_GMAC
+#define CONFIG_DESIGNWARE_ETH		/* GMAC can use designware driver */
+#define CONFIG_DW_AUTONEG
+#define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
+#define CONFIG_SYS_DCACHE_OFF		/* dw driver doesn't support dcache */
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#endif
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_TIMESTAMP		/* Needed by SNTP */
+#define CONFIG_CMD_DNS
+#define CONFIG_NETCONSOLE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+#define CONFIG_BOOTP_MAY_FAIL
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_DHCP_REQUEST_DELAY		50000
+#define CONFIG_CMD_ELF
+#endif
+
+#define CONFIG_DESIGNWARE_ETH		/* GMAC can use designware driver */
+#define CONFIG_DW_AUTONEG
+#define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
+#define CONFIG_SYS_DCACHE_OFF		/* dw driver doesn't support dcache */
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_TIMESTAMP		/* Needed by SNTP */
+#define CONFIG_CMD_DNS
+#define CONFIG_NETCONSOLE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+#define CONFIG_BOOTP_MAY_FAIL
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_DHCP_REQUEST_DELAY		50000
+#define CONFIG_CMD_ELF
+#endif
+
 #if !defined CONFIG_ENV_IS_IN_MMC && \
     !defined CONFIG_ENV_IS_IN_NAND && \
     !defined CONFIG_ENV_IS_IN_FAT && \
-- 
1.8.5.3

[U-Boot] [linux-sunxi] [PATCH v1 9/9] sunxi: add gmac Ethernet support

[Chen-Yu Tsai]

On Fri, Mar 14, 2014 at 6:33 PM, Ian Campbell <ijc@hellion.org.uk> wrote:
> Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in
> ldscripts" vs v2014.01.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Jens Kuske <jenskuske@gmail.com>
> Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
> ---
>  arch/arm/cpu/armv7/sunxi/board.c | 15 +++++++++
>  boards.cfg                       |  4 +--
>  drivers/net/Makefile             |  1 +
>  drivers/net/sunxi_gmac.c         | 34 ++++++++++++++++++++
>  include/configs/sunxi-common.h   | 68 ++++++++++++++++++++++++++++++++++++++++
>  5 files changed, 120 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/net/sunxi_gmac.c
[..]
> diff --git a/drivers/net/sunxi_gmac.c b/drivers/net/sunxi_gmac.c
> new file mode 100644
> index 0000000..432d7b2
> --- /dev/null
> +++ b/drivers/net/sunxi_gmac.c
> @@ -0,0 +1,34 @@
> +#include <common.h>
> +#include <netdev.h>
> +#include <miiphy.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/gpio.h>
> +
> +int sunxi_gmac_initialize(bd_t *bis)
> +{
> +       int pin;
> +       struct sunxi_ccm_reg *const ccm =
> +               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> +
> +       /* Set up clock gating */
> +       setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
> +
> +       /* Set MII clock */
> +       setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
> +               CCM_GMAC_CTRL_GPIT_RGMII);
> +
> +       /* Configure pin mux settings for GMAC */
> +       for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
> +               /* skip unused pins in RGMII mode */
> +               if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
> +                   continue;
> +               sunxi_gpio_set_cfgpin(pin, 5);
> +               sunxi_gpio_set_drv(pin, 3);
> +       }
> +
> +       designware_initialize(0, SUNXI_GMAC_BASE, 0x1, PHY_INTERFACE_MODE_RGMII);

Hi,

Thanks for working on this!

I see you left out all the CONFIG_RGMII ifdefs from this file. Not
sure if it's because you're aiming to support only the Cubietruck
first. I think you should keep them in the same patch. You can then
just add the appropriate config options when support of other A20
boards roll in.

There are 3 changes to the designware driver since u-boot-sunxi's
last merge (2014.1-rc1):

    50b0df8 net/designware: make driver compatible with data cache
    92a190a net/designware - switch driver to phylib usage
    74cb708 net/designware: add explicit reset of {tx|rx}_currdescnum

The move to phylib will likely break the current code. Maybe we could
merge 2014.4-rc1 in to fix it first.

Also, GMAC support depends on

    5a51af3 net/designware: Reduce DMA burst length

by Jens Kuske (jemk). Neither of us bothered to send this upstream yet.

Cheers
ChenYu


> +
> +       return 0;
> +}
[..]

[U-Boot] [linux-sunxi] [PATCH v1 9/9] sunxi: add gmac Ethernet support

[Ian Campbell]

On Fri, 2014-03-14 at 19:11 +0800, Chen-Yu Tsai wrote:
> Thanks for working on this!

No problem.

> I see you left out all the CONFIG_RGMII ifdefs from this file. Not
> sure if it's because you're aiming to support only the Cubietruck
> first.

Yes, exactly.

> I think you should keep them in the same patch. You can then
> just add the appropriate config options when support of other A20
> boards roll in.

I don't have any boards which require this, so I cannot test it. I'd
prefer to leave it to whoever adds support for the first such board to
put this stuff back in, it's a pretty trivial git diff invocation to
spot the needed bits.

> There are 3 changes to the designware driver since u-boot-sunxi's
> last merge (2014.1-rc1):
> 
>     50b0df8 net/designware: make driver compatible with data cache
>     92a190a net/designware - switch driver to phylib usage
>     74cb708 net/designware: add explicit reset of {tx|rx}_currdescnum
> 
> The move to phylib will likely break the current code. Maybe we could
> merge 2014.4-rc1 in to fix it first.

I'm happy to track any merges updates etc, sounds like at least this
patch will need some rebasing. Since this one is last I think it needn't
stop the rest going in (although I anticipate at least some review and
rebasing for all of it).

> Also, GMAC support depends on
> 
>     5a51af3 net/designware: Reduce DMA burst length
> 
> by Jens Kuske (jemk). Neither of us bothered to send this upstream yet.

I think I saw that in the sunxi tree but since it touched core code I
punted on it for now since I wasn't sure how to reconcile it with
non-sunxi platforms (i.e. what is the downside for other boards? Worse
performance?)

Thanks for your feedback.

Ian.

[U-Boot] [linux-sunxi] [PATCH v1 9/9] sunxi: add gmac Ethernet support

[Tom Rini]

On Fri, Mar 14, 2014 at 11:28:06AM +0000, Ian Campbell wrote:
> On Fri, 2014-03-14 at 19:11 +0800, Chen-Yu Tsai wrote:
[snip]
> > I think you should keep them in the same patch. You can then
> > just add the appropriate config options when support of other A20
> > boards roll in.
> 
> I don't have any boards which require this, so I cannot test it. I'd
> prefer to leave it to whoever adds support for the first such board to
> put this stuff back in, it's a pretty trivial git diff invocation to
> spot the needed bits.

I agree with this as well.

-- 
Tom
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[U-Boot] [linux-sunxi] [PATCH v1 9/9] sunxi: add gmac Ethernet support

[Ian Campbell]

On Fri, 2014-03-14 at 10:22 -0400, Tom Rini wrote:
> On Fri, Mar 14, 2014 at 11:28:06AM +0000, Ian Campbell wrote:
> > On Fri, 2014-03-14 at 19:11 +0800, Chen-Yu Tsai wrote:
> [snip]
> > > I think you should keep them in the same patch. You can then
> > > just add the appropriate config options when support of other A20
> > > boards roll in.
> > 
> > I don't have any boards which require this, so I cannot test it. I'd
> > prefer to leave it to whoever adds support for the first such board to
> > put this stuff back in, it's a pretty trivial git diff invocation to
> > spot the needed bits.
> 
> I agree with this as well.

With the request to add RGMII here or my reasons for not doing so?
(sorry if I'm being dense)

Ian.

[U-Boot] [linux-sunxi] [PATCH v1 9/9] sunxi: add gmac Ethernet support

[Tom Rini]

On Sun, Mar 16, 2014 at 03:09:01PM +0000, Ian Campbell wrote:
> On Fri, 2014-03-14 at 10:22 -0400, Tom Rini wrote:
> > On Fri, Mar 14, 2014 at 11:28:06AM +0000, Ian Campbell wrote:
> > > On Fri, 2014-03-14 at 19:11 +0800, Chen-Yu Tsai wrote:
> > [snip]
> > > > I think you should keep them in the same patch. You can then
> > > > just add the appropriate config options when support of other A20
> > > > boards roll in.
> > > 
> > > I don't have any boards which require this, so I cannot test it. I'd
> > > prefer to leave it to whoever adds support for the first such board to
> > > put this stuff back in, it's a pretty trivial git diff invocation to
> > > spot the needed bits.
> > 
> > I agree with this as well.
> 
> With the request to add RGMII here or my reasons for not doing so?
> (sorry if I'm being dense)

Sorry, I agree with your reason for not doing so.  Lets just add in what
we can test within the series and let the board(s) that needs it, add it.

-- 
Tom
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[U-Boot] [PATCH v1 9/9] sunxi: add gmac Ethernet support

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:51AM +0000, Ian Campbell wrote:

[snip]
> +#ifdef CONFIG_SUNXI_GMAC
> +#define CONFIG_DESIGNWARE_ETH		/* GMAC can use designware driver */
> +#define CONFIG_DW_AUTONEG
> +#define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
> +#define CONFIG_SYS_DCACHE_OFF		/* dw driver doesn't support dcache */

I think that was fixed recently..

> +
> +#ifdef CONFIG_CMD_NET
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_NFS
> +#define CONFIG_CMD_SNTP
> +#define CONFIG_TIMESTAMP		/* Needed by SNTP */
> +#define CONFIG_CMD_DNS
> +#define CONFIG_NETCONSOLE
> +#define CONFIG_BOOTP_SUBNETMASK
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_HOSTNAME
> +#define CONFIG_BOOTP_NISDOMAIN
> +#define CONFIG_BOOTP_BOOTPATH
> +#define CONFIG_BOOTP_BOOTFILESIZE
> +#define CONFIG_BOOTP_DNS
> +#define CONFIG_BOOTP_DNS2
> +#define CONFIG_BOOTP_SEND_HOSTNAME
> +#define CONFIG_BOOTP_NTPSERVER
> +#define CONFIG_BOOTP_TIMEOFFSET
> +#define CONFIG_BOOTP_MAY_FAIL
> +#define CONFIG_BOOTP_SERVERIP
> +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY		50000
> +#define CONFIG_CMD_ELF
> +#endif

We end up duplicating this in the next part of the hunk.

-- 
Tom
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[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:32AM +0000, Ian Campbell wrote:

> Hi,
> 
> This is my first cut at an upstreamable series based upon the
> https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> intention is to present a minimal starting point for upstreaming to
> which support for other processors, peripherals, boards etc can be
> added in the future. Therefore this has been stripped right back and
> currently supports only sun7i processors and the cubietruck
> board. Supported peripherals are UART, MMC and Ethernet.

First of all, yay.  Second, how hard would it be to add sun5i /
a13-olinuxino-micro support on top of this?  I ask since I've got one of
those sitting around here.  Would we be talking just board level things
or is sun5i vs sun7i a big deal?  Thanks!

-- 
Tom
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[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Ian Campbell]

On Fri, 2014-03-14 at 08:55 -0400, Tom Rini wrote:
> On Fri, Mar 14, 2014 at 10:33:32AM +0000, Ian Campbell wrote:
> 
> > Hi,
> > 
> > This is my first cut at an upstreamable series based upon the
> > https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> > intention is to present a minimal starting point for upstreaming to
> > which support for other processors, peripherals, boards etc can be
> > added in the future. Therefore this has been stripped right back and
> > currently supports only sun7i processors and the cubietruck
> > board. Supported peripherals are UART, MMC and Ethernet.
> 
> First of all, yay.  Second, how hard would it be to add sun5i /
> a13-olinuxino-micro support on top of this?  I ask since I've got one of
> those sitting around here.  Would we be talking just board level things
> or is sun5i vs sun7i a big deal?  Thanks!
> 

I think it would be pretty small, if you fetch my tree and git diff it
against the sunxi.git tree the diff bits with sun5i in them stand out
reasonably clearly.

I don't have such a platform myself though which is why I've not just
done it.

Ian.

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Tom Rini]

On Fri, Mar 14, 2014 at 01:59:38PM +0000, Ian Campbell wrote:
> On Fri, 2014-03-14 at 08:55 -0400, Tom Rini wrote:
> > On Fri, Mar 14, 2014 at 10:33:32AM +0000, Ian Campbell wrote:
> > 
> > > Hi,
> > > 
> > > This is my first cut at an upstreamable series based upon the
> > > https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> > > intention is to present a minimal starting point for upstreaming to
> > > which support for other processors, peripherals, boards etc can be
> > > added in the future. Therefore this has been stripped right back and
> > > currently supports only sun7i processors and the cubietruck
> > > board. Supported peripherals are UART, MMC and Ethernet.
> > 
> > First of all, yay.  Second, how hard would it be to add sun5i /
> > a13-olinuxino-micro support on top of this?  I ask since I've got one of
> > those sitting around here.  Would we be talking just board level things
> > or is sun5i vs sun7i a big deal?  Thanks!
> 
> I think it would be pretty small, if you fetch my tree and git diff it
> against the sunxi.git tree the diff bits with sun5i in them stand out
> reasonably clearly.
> 
> I don't have such a platform myself though which is why I've not just
> done it.

OK good, I think Albert and I might end up starting the sun4i/sun5i
stuff as those are the boards we've got sitting around.

-- 
Tom
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[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Albert ARIBAUD]

Hi Tom,

On Fri, 14 Mar 2014 10:19:27 -0400, Tom Rini <trini@ti.com> wrote:

> OK good, I think Albert and I might end up starting the sun4i/sun5i
> stuff as those are the boards we've got sitting around.

As I have a Mele A1000G (A31), that would be sun6i, not sun4i/sun5i --
and yes, I would like to contribute support for it.

Amicalement,
-- 
Albert.

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Hans de Goede]

Hi,

First of all: Ian: Many many thanks for working on this, you rock!

On 03/14/2014 04:01 PM, Albert ARIBAUD wrote:
> Hi Tom,
> 
> On Fri, 14 Mar 2014 10:19:27 -0400, Tom Rini <trini@ti.com> wrote:
> 
>> OK good, I think Albert and I might end up starting the sun4i/sun5i
>> stuff as those are the boards we've got sitting around.
> 
> As I have a Mele A1000G (A31), that would be sun6i, not sun4i/sun5i

So I'm very interested in getting sunxi support in upstream u-boot too, and
I've a ton of sunxi devices. I'll start working on doing a sun4i patch-set
on top of Ian's sun7i patch-set. Then Tom can start working on sun5i.

Tom, since I've started working on sunxi stuff 2 years ago I've gained a lot
of experience with these little SoCs so let me know if you hit some roadblock
and I can take a look.

Disclaimer I'm more of a kernel / device driver guy, all the low-level
RAM init (and having to think about where in memory to put all the bits)
is mostly new, so have some patience with me please :)

> and yes, I would like to contribute support for it.

If someone can start working on sun6i support that would be awesome.

My sunxi-next u-boot branch:
https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-next

Has some minimal patches by Maxime to get u-boot to run as a secondary
boot-loader, using allwinner's boot0 and boot1 as primary loader.

What we really want is to get a working SPL for sun6i, there are 2 ways
to get to a working SPL:

1) Use allwinners special USB boot mode called FEL, this way no MMC / NAND
reading code is necessary.
2) First get MMC to work using uboot as a secondary loader only, and
once we've working MMC code try to get a SPL which can read the
real u-boot directly from MMC.

And then for 2, there is the option to first get MMC for sun6i working in the
upstream Linux kernel, so that we know exactly what changes are needed compared
to sun5i / sun7i MMC (which are identical).

I've done a lot of work on the upstream kernel mmc host driver, and I actually
wanted to start looking into MMC for sun6i in the upstream kernel one of these
days. But now that Ian has published his awesome work to get sunxi support upstream,
my first priority is to get sun4i + sun5i support added on top of Ian's patches.

Regards,

Hans

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Hans de Goede]

Hi,

<snip>

>> and yes, I would like to contribute support for it.
> 
> If someone can start working on sun6i support that would be awesome.

p.s. One thing I forgot about sun6i / A31 support Oliver Schinagl has
some preliminary u-boot patches for it here:
https://github.com/oliv3r/u-boot-sunxi/commits/wip/a31

AFAIK these are based on various allwinner source dumps, and are untested
as Oliver does not have an A31 device.

Regards,

Hans

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Albert ARIBAUD]

Hi Ian,

On Fri, 14 Mar 2014 10:33:32 +0000, Ian Campbell <ijc@hellion.org.uk>
wrote:

> Hi,
> 
> This is my first cut at an upstreamable series based upon the
> https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> intention is to present a minimal starting point for upstreaming to
> which support for other processors, peripherals, boards etc can be
> added in the future. Therefore this has been stripped right back and
> currently supports only sun7i processors and the cubietruck
> board. Supported peripherals are UART, MMC and Ethernet.

I am not familiar with all of AllWinner's CPUs, so please forgive me if
I'm saying something stupid. Does sun7i support mean that A31 might be
supported as well? From what I understand, UART and Eth should be
somewhat common between A20 and A31, but MMC won't.

In any case, I am willing to try and add Mele A1000G U-Boot support
based on your series if that makes any sense. :)

Amicalement,
-- 
Albert.

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Maxime Ripard]

Hi Albert,

On Fri, Mar 14, 2014 at 02:02:29PM +0100, Albert ARIBAUD wrote:
> Hi Ian,
> 
> On Fri, 14 Mar 2014 10:33:32 +0000, Ian Campbell <ijc@hellion.org.uk>
> wrote:
> 
> > Hi,
> > 
> > This is my first cut at an upstreamable series based upon the
> > https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> > intention is to present a minimal starting point for upstreaming to
> > which support for other processors, peripherals, boards etc can be
> > added in the future. Therefore this has been stripped right back and
> > currently supports only sun7i processors and the cubietruck
> > board. Supported peripherals are UART, MMC and Ethernet.
> 
> I am not familiar with all of AllWinner's CPUs, so please forgive me if
> I'm saying something stupid. Does sun7i support mean that A31 might be
> supported as well? From what I understand, UART and Eth should be
> somewhat common between A20 and A31, but MMC won't.
> 
> In any case, I am willing to try and add Mele A1000G U-Boot support
> based on your series if that makes any sense. :)

Actually, between A20 and A31, a lot are common, but some IPs that are
of particular interest to u-boot aren't.

Most notably, the A20 and A31 share the same CPUs, interrupt
controller (GIC), timers (that are also shared with all the other
Allwinner SoCs), UART (designware's), ethernet (designware's GMAC
IP). MMC should be common too.

However, the A31 introduces a new RAM controller, a new DMA
controller, a new bus to interact with the PMIC, most notably.

So while we will be able to reuse some of that code, the A31 needs a
significant additional effort. The good news is that the newer
Allwinner SoCs seem to drop the old (and by old I mean
A10/A10s/A13/A20) IPs in favour of the one introduced in the A31. So
it's definitely worth doing this effort.

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Ian Campbell]

On Fri, 2014-03-14 at 14:02 +0100, Albert ARIBAUD wrote:
> Hi Ian,
> 
> On Fri, 14 Mar 2014 10:33:32 +0000, Ian Campbell <ijc@hellion.org.uk>
> wrote:
> 
> > Hi,
> > 
> > This is my first cut at an upstreamable series based upon the
> > https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> > intention is to present a minimal starting point for upstreaming to
> > which support for other processors, peripherals, boards etc can be
> > added in the future. Therefore this has been stripped right back and
> > currently supports only sun7i processors and the cubietruck
> > board. Supported peripherals are UART, MMC and Ethernet.
> 
> I am not familiar with all of AllWinner's CPUs, so please forgive me if
> I'm saying something stupid.

I probably should have included some context here anyway, since I guess
a lot of folks aren't familiar with Allwinner/sunxi.

> Does sun7i support mean that A31 might be
> supported as well?

sun7i == A20 processors while A31 is sun6i (yes, this seems somewhat
backwards to me as well), so there is no A31 support present in this
series. As Maxime says sun6i shares some but not all stuff with sun7i
and the bits which aren't still require work (which I believe people are
doing).

Ian.

>  From what I understand, UART and Eth should be
> somewhat common between A20 and A31, but MMC won't.
> 
> In any case, I am willing to try and add Mele A1000G U-Boot support
> based on your series if that makes any sense. :)
> 
> Amicalement,

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Tom Rini]

On Fri, Mar 14, 2014 at 10:33:32AM +0000, Ian Campbell wrote:

> Hi,
> 
> This is my first cut at an upstreamable series based upon the
> https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> intention is to present a minimal starting point for upstreaming to
> which support for other processors, peripherals, boards etc can be
> added in the future. Therefore this has been stripped right back and
> currently supports only sun7i processors and the cubietruck
> board. Supported peripherals are UART, MMC and Ethernet.

Some global comments:
- If you haven't already, make sure it's all checkpatch clean.
- Use the SPDX tags rather than including the GPL boilerplate.
- Please re-word the commit messages.  The "how we got here / where this
  is from" is fine for the cover letter.
- Magic numbers need to be defined.

Thanks!

-- 
Tom
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[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Ian Campbell]

On Fri, 2014-03-14 at 10:16 -0400, Tom Rini wrote:
> On Fri, Mar 14, 2014 at 10:33:32AM +0000, Ian Campbell wrote:
> 
> > Hi,
> > 
> > This is my first cut at an upstreamable series based upon the
> > https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> > intention is to present a minimal starting point for upstreaming to
> > which support for other processors, peripherals, boards etc can be
> > added in the future. Therefore this has been stripped right back and
> > currently supports only sun7i processors and the cubietruck
> > board. Supported peripherals are UART, MMC and Ethernet.
> 
> Some global comments:
> - If you haven't already, make sure it's all checkpatch clean.

I hadn't realised u-boot had a checkpatch. I shall do this.

> - Use the SPDX tags rather than including the GPL boilerplate.

Agreed, I already sent out a patch to sunxi.git to make this happen
there so I could sync it to this tree (so sunxi guys consider this a
ping on <1394161088-9835-1-git-send-email-ijc@hellion.org.uk> ;-))

I suppose I don't need to wait, but it was convenient to have a diff
which always shrank...

> - Please re-word the commit messages.  The "how we got here / where this
>   is from" is fine for the cover letter.

OK, that was mostly for my own reference. Mind if I put it at the end
after "---" so git am will strip it?

> - Magic numbers need to be defined.

Will do.

Thanks,
Ian.

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Tom Rini]

On Fri, Mar 14, 2014 at 03:04:28PM +0000, Ian Campbell wrote:
> On Fri, 2014-03-14 at 10:16 -0400, Tom Rini wrote:
> > On Fri, Mar 14, 2014 at 10:33:32AM +0000, Ian Campbell wrote:
> > 
> > > Hi,
> > > 
> > > This is my first cut at an upstreamable series based upon the
> > > https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> > > intention is to present a minimal starting point for upstreaming to
> > > which support for other processors, peripherals, boards etc can be
> > > added in the future. Therefore this has been stripped right back and
> > > currently supports only sun7i processors and the cubietruck
> > > board. Supported peripherals are UART, MMC and Ethernet.
> > 
> > Some global comments:
[snip]
> > - Please re-word the commit messages.  The "how we got here / where this
> >   is from" is fine for the cover letter.
> 
> OK, that was mostly for my own reference. Mind if I put it at the end
> after "---" so git am will strip it?

Yeah, that's a good idea.

> > - Magic numbers need to be defined.
> 
> Will do.

Thanks!

-- 
Tom
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[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Dennis Gilmore]

On Fri, 14 Mar 2014 10:16:42 -0400
Tom Rini <trini@ti.com> wrote:

> On Fri, Mar 14, 2014 at 10:33:32AM +0000, Ian Campbell wrote:
> 
> > Hi,
> > 
> > This is my first cut at an upstreamable series based upon the
> > https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> > intention is to present a minimal starting point for upstreaming to
> > which support for other processors, peripherals, boards etc can be
> > added in the future. Therefore this has been stripped right back and
> > currently supports only sun7i processors and the cubietruck
> > board. Supported peripherals are UART, MMC and Ethernet.
> 
> Some global comments:
> - If you haven't already, make sure it's all checkpatch clean.
> - Use the SPDX tags rather than including the GPL boilerplate.
> - Please re-word the commit messages.  The "how we got here / where
> this is from" is fine for the cover letter.
> - Magic numbers need to be defined.

I have a quick request also, Please incorporate the ongoing generic
distro work as most if not all of the sunxi systems I know of are
targets for generic distros.

Dennis

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Hans de Goede]

Hi Dennis,

On 03/14/2014 09:17 PM, Dennis Gilmore wrote:
> On Fri, 14 Mar 2014 10:16:42 -0400
> Tom Rini <trini@ti.com> wrote:
> 
>> On Fri, Mar 14, 2014 at 10:33:32AM +0000, Ian Campbell wrote:
>>
>>> Hi,
>>>
>>> This is my first cut at an upstreamable series based upon the
>>> https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
>>> intention is to present a minimal starting point for upstreaming to
>>> which support for other processors, peripherals, boards etc can be
>>> added in the future. Therefore this has been stripped right back and
>>> currently supports only sun7i processors and the cubietruck
>>> board. Supported peripherals are UART, MMC and Ethernet.
>>
>> Some global comments:
>> - If you haven't already, make sure it's all checkpatch clean.
>> - Use the SPDX tags rather than including the GPL boilerplate.
>> - Please re-word the commit messages.  The "how we got here / where
>> this is from" is fine for the cover letter.
>> - Magic numbers need to be defined.
> 
> I have a quick request also, Please incorporate the ongoing generic
> distro work as most if not all of the sunxi systems I know of are
> targets for generic distros.

No worries, I'll be following this closely (and contributing to it)
and I'll make sure this gets added. Do you've some pointers for
docs about this, or example patches for other boards ?

Regards,

Hans

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Ian Campbell]

On Fri, 2014-03-14 at 15:17 -0500, Dennis Gilmore wrote:
> On Fri, 14 Mar 2014 10:16:42 -0400
> Tom Rini <trini@ti.com> wrote:
> 
> > On Fri, Mar 14, 2014 at 10:33:32AM +0000, Ian Campbell wrote:
> > 
> > > Hi,
> > > 
> > > This is my first cut at an upstreamable series based upon the
> > > https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> > > intention is to present a minimal starting point for upstreaming to
> > > which support for other processors, peripherals, boards etc can be
> > > added in the future. Therefore this has been stripped right back and
> > > currently supports only sun7i processors and the cubietruck
> > > board. Supported peripherals are UART, MMC and Ethernet.
> > 
> > Some global comments:
> > - If you haven't already, make sure it's all checkpatch clean.
> > - Use the SPDX tags rather than including the GPL boilerplate.
> > - Please re-word the commit messages.  The "how we got here / where
> > this is from" is fine for the cover letter.
> > - Magic numbers need to be defined.
> 
> I have a quick request also, Please incorporate the ongoing generic
> distro work as most if not all of the sunxi systems I know of are
> targets for generic distros.

This: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/180540 ?

Sure.

Ian.

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Marek Vasut]

On Friday, March 14, 2014 at 11:33:32 AM, Ian Campbell wrote:
> Hi,
> 
> This is my first cut at an upstreamable series based upon the
> https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree. The
> intention is to present a minimal starting point for upstreaming to
> which support for other processors, peripherals, boards etc can be
> added in the future. Therefore this has been stripped right back and
> currently supports only sun7i processors and the cubietruck
> board. Supported peripherals are UART, MMC and Ethernet.
> 
> The code here is from sunxi.git#sunxi[0] changeset d854c4de2f57 "arm:
> Handle .gnu.hash section in ldscripts" and applied to u-boot v2014.01.
> 
> This series can also be found at:
> 
>     git://gitorious.org/ijc/u-boot.git sunxi-mainlining-v1

Nice, finally!

Best regards,
Marek Vasut

[U-Boot] [PATCH v1 0/9] sunxi: initial upstreamining effort

[Henrik Nordström]

fre 2014-03-14 klockan 10:33 +0000 skrev Ian Campbell:

> This is my first cut at an upstreamable series based upon the
> https://github.com/linux-sunxi/u-boot-sunxi.git#sunxi tree.

Thanks for picking this up. Much needed.

Regards
Henrik