[U-Boot] [PATCH v5 2/2] socfpga: Adding DesignWare watchdog support

[U-Boot] [PATCH v5 2/2] socfpga: Adding DesignWare watchdog support

[Chin Liang See]

To enable the DesignWare watchdog support at SOCFPGA
Cyclone V dev kit.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
---
Changes for v5
- Updated to latest code branch
Changes for v4
- Updated to latest code branch
Changes for v3
- Split to 2 series patch
Changes for v2
- Enable this driver at socfpga_cyclone5 board
---
 .../include/asm/arch-socfpga/socfpga_base_addrs.h  |    1 +
 include/configs/socfpga_cyclone5.h                 |   14 ++++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
index f564046..f2ecbbd 100644
--- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
+++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
@@ -11,6 +11,7 @@
 #define SOCFPGA_UART0_ADDRESS 0xffc02000
 #define SOCFPGA_UART1_ADDRESS 0xffc03000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 0254249..34291c7 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -206,6 +206,17 @@
 #define CONFIG_ENV_IS_NOWHERE
 
 /*
+ * L4 Watchdog
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	2000
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+/* Clocks source frequency to watchdog timer */
+#define CONFIG_DW_WDT_CLOCK_KHZ		25000
+
+
+/*
  * SPL "Second Program Loader" aka Initial Software
  */
 
@@ -237,4 +248,7 @@
 /* Support for lib/libgeneric.o in SPL binary */
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 
+/* Support for watchdog */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
 #endif	/* __CONFIG_H */
-- 
1.7.9.5

[U-Boot] [PATCH v5 2/2] socfpga: Adding DesignWare watchdog support

[Albert ARIBAUD]

Hi Chin,

On Tue, 10 Jun 2014 01:11:04 -0500, Chin Liang See <clsee@altera.com>
wrote:

> To enable the DesignWare watchdog support at SOCFPGA
> Cyclone V dev kit.
> 
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Anatolij Gustschin <agust@denx.de>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> Cc: Heiko Schocher <hs@denx.de>
> Cc: Tom Rini <trini@ti.com>
> ---
> Changes for v5
> - Updated to latest code branch
> Changes for v4
> - Updated to latest code branch
> Changes for v3
> - Split to 2 series patch
> Changes for v2
> - Enable this driver at socfpga_cyclone5 board
> ---
>  .../include/asm/arch-socfpga/socfpga_base_addrs.h  |    1 +
>  include/configs/socfpga_cyclone5.h                 |   14 ++++++++++++++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
> index f564046..f2ecbbd 100644
> --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
> +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
> @@ -11,6 +11,7 @@
>  #define SOCFPGA_UART0_ADDRESS 0xffc02000
>  #define SOCFPGA_UART1_ADDRESS 0xffc03000
>  #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
> +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
>  #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
>  #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
>  #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
> diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
> index 0254249..34291c7 100644
> --- a/include/configs/socfpga_cyclone5.h
> +++ b/include/configs/socfpga_cyclone5.h
> @@ -206,6 +206,17 @@
>  #define CONFIG_ENV_IS_NOWHERE
>  
>  /*
> + * L4 Watchdog
> + */
> +#define CONFIG_HW_WATCHDOG
> +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	2000
> +#define CONFIG_DESIGNWARE_WATCHDOG
> +#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
> +/* Clocks source frequency to watchdog timer */
> +#define CONFIG_DW_WDT_CLOCK_KHZ		25000
> +
> +
> +/*
>   * SPL "Second Program Loader" aka Initial Software
>   */
>  
> @@ -237,4 +248,7 @@
>  /* Support for lib/libgeneric.o in SPL binary */
>  #define CONFIG_SPL_LIBGENERIC_SUPPORT
>  
> +/* Support for watchdog */
> +#define CONFIG_SPL_WATCHDOG_SUPPORT
> +
>  #endif	/* __CONFIG_H */

Applied to u-boot-arm/master, thanks!

Amicalement,
-- 
Albert.