[U-Boot] [PATCH] arch/arm: Add individual TLB size support.

[U-Boot] [PATCH] arch/arm: Add individual TLB size support.

[Xiubo Li]

This adds CONFIG_TLB_SIZE for individual board, whose TLB size maybe
larger than PGTABLE_SIZE.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
 arch/arm/lib/board.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index dc34190..b7327ce 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -353,7 +353,11 @@ void board_init_f(ulong bootflag)
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	/* reserve TLB table */
+#ifdef CONFIG_TLB_SIZE
+	gd->arch.tlb_size = CONFIG_TLB_SIZE;
+#else
 	gd->arch.tlb_size = PGTABLE_SIZE;
+#endif
 	addr -= gd->arch.tlb_size;
 
 	/* round down to next 64 kB limit */
-- 
1.8.5

[U-Boot] [PATCH] arch/arm: Add individual TLB size support.

[Albert ARIBAUD]

Hi Xiubo,

On Mon, 7 Jul 2014 13:19:11 +0800, Xiubo Li <Li.Xiubo@freescale.com>
wrote:

> This adds CONFIG_TLB_SIZE for individual board, whose TLB size maybe
> larger than PGTABLE_SIZE.
> 
> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> ---
>  arch/arm/lib/board.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
> index dc34190..b7327ce 100644
> --- a/arch/arm/lib/board.c
> +++ b/arch/arm/lib/board.c
> @@ -353,7 +353,11 @@ void board_init_f(ulong bootflag)
>  
>  #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
>  	/* reserve TLB table */
> +#ifdef CONFIG_TLB_SIZE
> +	gd->arch.tlb_size = CONFIG_TLB_SIZE;
> +#else
>  	gd->arch.tlb_size = PGTABLE_SIZE;
> +#endif
>  	addr -= gd->arch.tlb_size;
>  
>  	/* round down to next 64 kB limit */

There is no code in current mainline which defines CONFIG_TLB_SIZE;
that makes the patch a dead code addition.

Besides, what's the point of this as opposed to, e.g., just defining the
right PGTABLE_SIZE, or renaming PGTABLE_SIZE as CONFIG_TLB_SIZE?

Amicalement,
-- 
Albert.

[U-Boot] [PATCH] arch/arm: Add individual TLB size support.

[Li.Xiubo at freescale.com]

Hi Albert,

> Subject: Re: [PATCH] arch/arm: Add individual TLB size support.
> 
> Hi Xiubo,
> 
> On Mon, 7 Jul 2014 13:19:11 +0800, Xiubo Li <Li.Xiubo@freescale.com>
> wrote:
> 
> > This adds CONFIG_TLB_SIZE for individual board, whose TLB size maybe
> > larger than PGTABLE_SIZE.
> >
> > Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> > ---
> >  arch/arm/lib/board.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
> > index dc34190..b7327ce 100644
> > --- a/arch/arm/lib/board.c
> > +++ b/arch/arm/lib/board.c
> > @@ -353,7 +353,11 @@ void board_init_f(ulong bootflag)
> >
> >  #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
> >  	/* reserve TLB table */
> > +#ifdef CONFIG_TLB_SIZE
> > +	gd->arch.tlb_size = CONFIG_TLB_SIZE;
> > +#else
> >  	gd->arch.tlb_size = PGTABLE_SIZE;
> > +#endif
> >  	addr -= gd->arch.tlb_size;
> >
> >  	/* round down to next 64 kB limit */
> 
> There is no code in current mainline which defines CONFIG_TLB_SIZE;
> that makes the patch a dead code addition.
>

Yes, this will be used by our LS1 SoC first, and it is still doing
The upstream.

 
> Besides, what's the point of this as opposed to, e.g., just defining the
> right PGTABLE_SIZE, or renaming PGTABLE_SIZE as CONFIG_TLB_SIZE?
> 

We'll add the LPAE support in uboot and need more space for tlb.

Thanks very much,

BRs
Xiubo

[U-Boot] [PATCH] arch/arm: Add individual TLB size support.

[Albert ARIBAUD]

Hi Li.Xiubo at freescale.com,

On Wed, 10 Sep 2014 03:10:27 +0000, "Li.Xiubo at freescale.com"
<Li.Xiubo@freescale.com> wrote:

> Hi Albert,
> 
> > Subject: Re: [PATCH] arch/arm: Add individual TLB size support.
> > 
> > Hi Xiubo,
> > 
> > On Mon, 7 Jul 2014 13:19:11 +0800, Xiubo Li <Li.Xiubo@freescale.com>
> > wrote:
> > 
> > > This adds CONFIG_TLB_SIZE for individual board, whose TLB size maybe
> > > larger than PGTABLE_SIZE.
> > >
> > > Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> > > ---
> > >  arch/arm/lib/board.c | 4 ++++
> > >  1 file changed, 4 insertions(+)
> > >
> > > diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
> > > index dc34190..b7327ce 100644
> > > --- a/arch/arm/lib/board.c
> > > +++ b/arch/arm/lib/board.c
> > > @@ -353,7 +353,11 @@ void board_init_f(ulong bootflag)
> > >
> > >  #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
> > >  	/* reserve TLB table */
> > > +#ifdef CONFIG_TLB_SIZE
> > > +	gd->arch.tlb_size = CONFIG_TLB_SIZE;
> > > +#else
> > >  	gd->arch.tlb_size = PGTABLE_SIZE;
> > > +#endif
> > >  	addr -= gd->arch.tlb_size;
> > >
> > >  	/* round down to next 64 kB limit */
> > 
> > There is no code in current mainline which defines CONFIG_TLB_SIZE;
> > that makes the patch a dead code addition.
> >
> 
> Yes, this will be used by our LS1 SoC first, and it is still doing
> The upstream.

Then please sumbit this patch as part of the LS1 SoC support series,
where the code it creates will actually be used.
 
> > Besides, what's the point of this as opposed to, e.g., just defining the
> > right PGTABLE_SIZE, or renaming PGTABLE_SIZE as CONFIG_TLB_SIZE?
> > 
> 
> We'll add the LPAE support in uboot and need more space for tlb.

I still don't get it. Is gd->arch.tlb_size the size of a page table or
of a translation lookahead buffer?

> Thanks very much,
> 
> BRs
> Xiubo

Amicalement,
-- 
Albert.

[U-Boot] [PATCH] arch/arm: Add individual TLB size support.

[Albert ARIBAUD]

Hi Albert,

On Thu, 11 Sep 2014 17:55:00 +0200, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:

> Hi Li.Xiubo at freescale.com,
> 
> On Wed, 10 Sep 2014 03:10:27 +0000, "Li.Xiubo at freescale.com"
> <Li.Xiubo@freescale.com> wrote:
> 
> > Hi Albert,
> > 
> > > Subject: Re: [PATCH] arch/arm: Add individual TLB size support.
> > > 
> > > Hi Xiubo,
> > > 
> > > On Mon, 7 Jul 2014 13:19:11 +0800, Xiubo Li <Li.Xiubo@freescale.com>
> > > wrote:
> > > 
> > > > This adds CONFIG_TLB_SIZE for individual board, whose TLB size maybe
> > > > larger than PGTABLE_SIZE.
> > > >
> > > > Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
> > > > ---
> > > >  arch/arm/lib/board.c | 4 ++++
> > > >  1 file changed, 4 insertions(+)
> > > >
> > > > diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
> > > > index dc34190..b7327ce 100644
> > > > --- a/arch/arm/lib/board.c
> > > > +++ b/arch/arm/lib/board.c
> > > > @@ -353,7 +353,11 @@ void board_init_f(ulong bootflag)
> > > >
> > > >  #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
> > > >  	/* reserve TLB table */
> > > > +#ifdef CONFIG_TLB_SIZE
> > > > +	gd->arch.tlb_size = CONFIG_TLB_SIZE;
> > > > +#else
> > > >  	gd->arch.tlb_size = PGTABLE_SIZE;
> > > > +#endif
> > > >  	addr -= gd->arch.tlb_size;
> > > >
> > > >  	/* round down to next 64 kB limit */
> > > 
> > > There is no code in current mainline which defines CONFIG_TLB_SIZE;
> > > that makes the patch a dead code addition.
> > >
> > 
> > Yes, this will be used by our LS1 SoC first, and it is still doing
> > The upstream.
> 
> Then please sumbit this patch as part of the LS1 SoC support series,
> where the code it creates will actually be used.
>  
> > > Besides, what's the point of this as opposed to, e.g., just defining the
> > > right PGTABLE_SIZE, or renaming PGTABLE_SIZE as CONFIG_TLB_SIZE?
> > > 
> > 
> > We'll add the LPAE support in uboot and need more space for tlb.
> 
> I still don't get it. Is gd->arch.tlb_size the size of a page table or
> of a translation lookahead buffer?

Ping on both points. Meanwhile I've put the patch in 'Changes
Requested' state.

> > Thanks very much,
> > 
> > BRs
> > Xiubo
> 
> Amicalement,

Amicalement,
-- 
Albert.