From mboxrd@z Thu Jan  1 00:00:00 1970
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Wed, 13 Sep 2017 22:07:43 +0200
Subject: [U-Boot] [U-Boot,
	6/8] clk: rockchip: Add rk3368 Saradc clock support
In-Reply-To: <1505302336-74720-1-git-send-email-david.wu@rock-chips.com>
References: <1505302336-74720-1-git-send-email-david.wu@rock-chips.com>
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> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
> Saradc integer divider control register is 8-bits width.
> 
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>  arch/arm/include/asm/arch-rockchip/cru_rk3368.h |  5 ++++
>  drivers/clk/rockchip/clk_rk3368.c               | 32 +++++++++++++++++++++++++
>  2 files changed, 37 insertions(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>