From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F8B2C05027 for ; Sun, 19 Feb 2023 06:46:57 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C1426857DC; Sun, 19 Feb 2023 07:46:54 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id D32FB857DF; Sun, 19 Feb 2023 07:46:53 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E24ED85131 for ; Sun, 19 Feb 2023 07:46:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=peterlin@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 31J6kXXW032784; Sun, 19 Feb 2023 14:46:33 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from APC323 (10.0.12.98) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Sun, 19 Feb 2023 14:46:32 +0800 Date: Sun, 19 Feb 2023 14:41:41 +0000 From: Yu-Chien Peter Lin To: Heinrich Schuchardt CC: , , , "Samuel Holland" , Subject: Re: [RFC PATCH v3] doc: arch: Add document for RISC-V architecture Message-ID: References: <20230214101851.11648-1-peterlin@andestech.com> <8810dffc-76f2-33e0-69a9-5784f900bbf3@gmx.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <8810dffc-76f2-33e0-69a9-5784f900bbf3@gmx.de> User-Agent: Mutt/2.2.9 (2022-11-12) X-Originating-IP: [10.0.12.98] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 31J6kXXW032784 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Fri, Feb 17, 2023 at 02:26:17PM +0100, Heinrich Schuchardt wrote: > On 2/14/23 11:18, Yu Chien Peter Lin wrote: > > This patch adds a brief introduction to the RISC-V architecture and > > the typical boot process used on a variety of RISC-V platforms. > > > > Signed-off-by: Yu Chien Peter Lin > > Reviewed-by: Samuel Holland > > Reviewed-by: Simon Glass > > Reviewed-by: Rick Chen > > --- > > Changes v1 -> v2 > > - Use 'boot phases' rather than 'boot stages' > > - Pick up Samuel and Simon's RB tags > > Changes v2 -> v3 > > - Follow the suggestion by Heinrich [1] > > - Add the document as an entry of Andes maintainer in MAINTAINERS > > - Add some pointers to OpenSBI document > > > > [1] https://patchwork.ozlabs.org/project/uboot/patch/20230212070053.14800-1-peterlin@andestech.com/ > > --- > > MAINTAINERS | 1 + > > doc/arch/index.rst | 1 + > > doc/arch/riscv.rst | 74 ++++++++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 76 insertions(+) > > create mode 100644 doc/arch/riscv.rst > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index b9c505d5fa..5eb79faf29 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1292,6 +1292,7 @@ S: Maintained > > T: git https://source.denx.de/u-boot/custodians/u-boot-riscv.git > > F: arch/riscv/ > > F: cmd/riscv/ > > +F: doc/arch/riscv.rst > > F: doc/usage/sbi.rst > > F: drivers/sysreset/sysreset_sbi.c > > F: drivers/timer/andes_plmt_timer.c > > diff --git a/doc/arch/index.rst b/doc/arch/index.rst > > index b3e85f9bf3..b8da4b8c8e 100644 > > --- a/doc/arch/index.rst > > +++ b/doc/arch/index.rst > > @@ -11,6 +11,7 @@ Architecture-specific doc > > m68k > > mips > > nios2 > > + riscv > > sandbox/index > > sh > > x86 > > diff --git a/doc/arch/riscv.rst b/doc/arch/riscv.rst > > new file mode 100644 > > index 0000000000..10bf3e6849 > > --- /dev/null > > +++ b/doc/arch/riscv.rst > > @@ -0,0 +1,74 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > +.. Copyright (C) 2023, Yu Chien Peter Lin > > + > > +RISC-V > > +====== > > + > > +Overview > > +-------- > > + > > +This document outlines the U-Boot boot process for the RISC-V architecture. > > +RISC-V is an open-source instruction set architecture (ISA) based on the > > +principles of reduced instruction set computing (RISC). It has been designed > > +to be flexible and customizable, allowing it to be adapted to different use > > +cases, from embedded systems to high performance servers. > > + > > +Typical Boot Process > > +-------------------- > > + > > +U-Boot can run in either M-mode or S-mode, depending on whether it runs before > > +the initialization of the firmware providing SBI (Supervisor Binary Interface). > > +The firmware is necessary in the RISC-V boot process as it serves as a SEE > > +(Supervisor Execution Environment) to handle exceptions for the S-mode U-Boot > > +or Operating System. > > + > > +In between the boot phases, the hartid is passed through the a0 register, and > > +the start address of the devicetree is passed through the a1 register. > > + > > +As a reference, OpenSBI is an SBI implementation that can be used with U-Boot > > +in different modes, see the `OpenSBI firmware document `_ for more details. > > + > > +M-mode U-Boot > > +^^^^^^^^^^^^^ > > + > > +When running in M-mode U-Boot, it will load the payload image (e.g. `fw_payload `_) > > +which contains the firmware and the S-mode Operating System; in this case, you > > +can use mkimage to package the payload image into an uImage format, and boot it > > +using the bootm command. > > + > > +The following diagram illustrates the boot process:: > > + > > + <-----------( M-mode )----------><--( S-mode )--> > > + +----------+ +--------------+ +------------+ > > + | U-Boot |-->| SBI firmware |--->| OS | > > + +----------+ +--------------+ +------------+ > > + > > +To examine the boot process with the QEMU virt machine, you can follow the > > +steps in the "Building U-Boot" section of the following document: > > +:doc:`../board/emulation/qemu-riscv.rst` > > This patch does not build. '.rst' has to removed here. > > doc/arch/riscv.rst:46:unknown document: ../board/emulation/qemu-riscv.rst > make[1]: *** [doc/Makefile:70: htmldocs] Error 2 > make: *** [Makefile:2348: htmldocs] Error 2 > > Please, execute the build process as described in > > https://u-boot.readthedocs.io/en/latest/build/documentation.html#html-documentation > > for testing your documentation patches. > > I will fix this issue when merging. Thank you for the contribution. Hi Heinrich, Thanks for the pointer, I will make sure it builds on my local next time. Best regards, Peter Lin > Best regards > > Heinrich