* [PATCH 1/2] riscv: Rename Andes cpu and board names
@ 2023-02-09 8:34 Leo Yu-Chi Liang
2023-02-09 8:34 ` [PATCH 2/2] riscv: ae350: Adjust the memory layout of ae350 Leo Yu-Chi Liang
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Leo Yu-Chi Liang @ 2023-02-09 8:34 UTC (permalink / raw)
To: u-boot; +Cc: rick, peterlin, Leo Yu-Chi Liang
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/Kconfig | 8 ++++----
arch/riscv/cpu/{ax25 => andesv5}/Kconfig | 0
arch/riscv/cpu/{ax25 => andesv5}/Makefile | 0
arch/riscv/cpu/{ax25 => andesv5}/cache.c | 0
arch/riscv/cpu/{ax25 => andesv5}/cpu.c | 0
arch/riscv/cpu/{ax25 => andesv5}/spl.c | 0
arch/riscv/dts/Makefile | 2 +-
board/AndesTech/{ax25-ae350 => ae350}/Kconfig | 8 ++++----
.../AndesTech/{ax25-ae350 => ae350}/MAINTAINERS | 6 +++---
board/AndesTech/{ax25-ae350 => ae350}/Makefile | 2 +-
.../{ax25-ae350/ax25-ae350.c => ae350/ae350.c} | 0
configs/ae350_rv32_defconfig | 2 +-
configs/ae350_rv32_spl_defconfig | 2 +-
configs/ae350_rv32_spl_xip_defconfig | 2 +-
configs/ae350_rv32_xip_defconfig | 2 +-
configs/ae350_rv64_defconfig | 2 +-
configs/ae350_rv64_spl_defconfig | 2 +-
configs/ae350_rv64_spl_xip_defconfig | 2 +-
configs/ae350_rv64_xip_defconfig | 2 +-
.../AndesTech/{ax25-ae350.rst => ae350.rst} | 16 ++++++++--------
doc/board/AndesTech/index.rst | 2 +-
include/configs/{ax25-ae350.h => ae350.h} | 0
22 files changed, 30 insertions(+), 30 deletions(-)
rename arch/riscv/cpu/{ax25 => andesv5}/Kconfig (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/Makefile (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/cache.c (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/cpu.c (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/spl.c (100%)
rename board/AndesTech/{ax25-ae350 => ae350}/Kconfig (88%)
rename board/AndesTech/{ax25-ae350 => ae350}/MAINTAINERS (80%)
rename board/AndesTech/{ax25-ae350 => ae350}/Makefile (87%)
rename board/AndesTech/{ax25-ae350/ax25-ae350.c => ae350/ae350.c} (100%)
rename doc/board/AndesTech/{ax25-ae350.rst => ae350.rst} (98%)
rename include/configs/{ax25-ae350.h => ae350.h} (100%)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ebc4bef220..48ca4ff4c4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -8,8 +8,8 @@ choice
prompt "Target select"
optional
-config TARGET_AX25_AE350
- bool "Support ax25-ae350"
+config TARGET_AE350
+ bool "Support ae350"
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
@@ -58,7 +58,7 @@ config SPL_SYS_DCACHE_OFF
Do not enable data cache in SPL.
# board-specific options below
-source "board/AndesTech/ax25-ae350/Kconfig"
+source "board/AndesTech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
@@ -67,7 +67,7 @@ source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below
-source "arch/riscv/cpu/ax25/Kconfig"
+source "arch/riscv/cpu/andesv5/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/andesv5/Kconfig
similarity index 100%
rename from arch/riscv/cpu/ax25/Kconfig
rename to arch/riscv/cpu/andesv5/Kconfig
diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/andesv5/Makefile
similarity index 100%
rename from arch/riscv/cpu/ax25/Makefile
rename to arch/riscv/cpu/andesv5/Makefile
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/andesv5/cache.c
similarity index 100%
rename from arch/riscv/cpu/ax25/cache.c
rename to arch/riscv/cpu/andesv5/cache.c
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
similarity index 100%
rename from arch/riscv/cpu/ax25/cpu.c
rename to arch/riscv/cpu/andesv5/cpu.c
diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/andesv5/spl.c
similarity index 100%
rename from arch/riscv/cpu/ax25/spl.c
rename to arch/riscv/cpu/andesv5/spl.c
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 5c15a0f303..c576c55767 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ae350/Kconfig
similarity index 88%
rename from board/AndesTech/ax25-ae350/Kconfig
rename to board/AndesTech/ae350/Kconfig
index 4bb33b0793..75815bf99a 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ae350/Kconfig
@@ -1,10 +1,10 @@
-if TARGET_AX25_AE350
+if TARGET_AE350
config SYS_CPU
- default "ax25"
+ default "andesv5"
config SYS_BOARD
- default "ax25-ae350"
+ default "ae350"
config SYS_VENDOR
default "AndesTech"
@@ -13,7 +13,7 @@ config SYS_SOC
default "ae350"
config SYS_CONFIG_NAME
- default "ax25-ae350"
+ default "ae350"
config ENV_SIZE
default 0x2000 if ENV_IS_IN_SPI_FLASH
diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ae350/MAINTAINERS
similarity index 80%
rename from board/AndesTech/ax25-ae350/MAINTAINERS
rename to board/AndesTech/ae350/MAINTAINERS
index eebee167c3..ead8e0e2af 100644
--- a/board/AndesTech/ax25-ae350/MAINTAINERS
+++ b/board/AndesTech/ae350/MAINTAINERS
@@ -1,8 +1,8 @@
-AX25-AE350 BOARD
+AE350 BOARD
M: Rick Chen <rick@andestech.com>
S: Maintained
-F: board/AndesTech/ax25-ae350/
-F: include/configs/ax25-ae350.h
+F: board/AndesTech/ae350/
+F: include/configs/ae350.h
F: configs/ae350_rv32_defconfig
F: configs/ae350_rv64_defconfig
F: configs/ae350_rv32_xip_defconfig
diff --git a/board/AndesTech/ax25-ae350/Makefile b/board/AndesTech/ae350/Makefile
similarity index 87%
rename from board/AndesTech/ax25-ae350/Makefile
rename to board/AndesTech/ae350/Makefile
index 0e4ba8d702..705ae43af5 100644
--- a/board/AndesTech/ax25-ae350/Makefile
+++ b/board/AndesTech/ae350/Makefile
@@ -3,4 +3,4 @@
# Copyright (C) 2017 Andes Technology Corporation.
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
-obj-y := ax25-ae350.o
+obj-y := ae350.o
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ae350/ae350.c
similarity index 100%
rename from board/AndesTech/ax25-ae350/ax25-ae350.c
rename to board/AndesTech/ae350/ae350.c
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index fd1bf5fa4f..953cd0700b 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 4d3623a894..d61f7f5d1d 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -8,7 +8,7 @@ CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
CONFIG_RISCV_SMODE=y
# CONFIG_AVAILABLE_HARTS is not set
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index a076b77834..e59ba0c38a 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -9,7 +9,7 @@ CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_SPL_XIP=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index da1bd2b10b..926632137d 100644
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index 959258176a..3c18562ad4 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index 0217027e6d..cb69514a7e 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -8,7 +8,7 @@ CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
# CONFIG_AVAILABLE_HARTS is not set
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index 5a1fa8b6a1..e0773fa0aa 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -9,7 +9,7 @@ CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_SPL_XIP=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
index c3fcbf3d28..0d467b9836 100644
--- a/configs/ae350_rv64_xip_defconfig
+++ b/configs/ae350_rv64_xip_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_XIP=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/doc/board/AndesTech/ax25-ae350.rst b/doc/board/AndesTech/ae350.rst
similarity index 98%
rename from doc/board/AndesTech/ax25-ae350.rst
rename to doc/board/AndesTech/ae350.rst
index b46f427f4b..42a2b4d0b5 100644
--- a/doc/board/AndesTech/ax25-ae350.rst
+++ b/doc/board/AndesTech/ae350.rst
@@ -1,20 +1,20 @@
.. SPDX-License-Identifier: GPL-2.0+
-AX25-AE350
-==========
+AE350
+======
-AE350 is the mainline SoC produced by Andes Technology using AX25 CPU core
-base on RISC-V architecture.
+AE350 is the mainline SoC produced by Andes Technology using AndesV5 CPU core
+based on RISC-V architecture.
AE350 has integrated both AHB and APB bus and many periphals for application
and product development.
-AX25-AE350 is the SoC with AE350 hardcore CPU.
+AndesV5 is Andes CPU IP family that adopts RISC-V architecture.
-AX25 is Andes CPU IP to adopt RISC-V architecture.
+AndesV5 family includes 25, 27, 45 series.
-AX25 Features
--------------
+25-Series Features
+------------------
CPU Core
- 5-stage in-order execution pipeline
diff --git a/doc/board/AndesTech/index.rst b/doc/board/AndesTech/index.rst
index d8f7d155fc..cacc5791a9 100644
--- a/doc/board/AndesTech/index.rst
+++ b/doc/board/AndesTech/index.rst
@@ -7,4 +7,4 @@ Andes Tech
:maxdepth: 2
adp-ag101p
- ax25-ae350
+ ae350
diff --git a/include/configs/ax25-ae350.h b/include/configs/ae350.h
similarity index 100%
rename from include/configs/ax25-ae350.h
rename to include/configs/ae350.h
--
2.38.0.68.ge85701b4af.dirty
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] riscv: ae350: Adjust the memory layout of ae350
2023-02-09 8:34 [PATCH 1/2] riscv: Rename Andes cpu and board names Leo Yu-Chi Liang
@ 2023-02-09 8:34 ` Leo Yu-Chi Liang
[not found] ` <PU1PR03MB299707FBC7804F51D8384466C1DD9@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-12 15:57 ` [PATCH 1/2] riscv: Rename Andes cpu and board names Yu-Chien Peter Lin
[not found] ` <PU1PR03MB29973BA93E3E6994D7DE5959C1DD9@PU1PR03MB2997.apcprd03.prod.outlook.com>
2 siblings, 1 reply; 5+ messages in thread
From: Leo Yu-Chi Liang @ 2023-02-09 8:34 UTC (permalink / raw)
To: u-boot; +Cc: rick, peterlin, Leo Yu-Chi Liang
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
configs/ae350_rv32_spl_defconfig | 6 +++---
configs/ae350_rv32_spl_xip_defconfig | 6 +++---
configs/ae350_rv64_spl_defconfig | 6 +++---
configs/ae350_rv64_spl_xip_defconfig | 6 +++---
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index d61f7f5d1d..fd9f100be3 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -1,7 +1,9 @@
CONFIG_RISCV=y
-CONFIG_TEXT_BASE=0x01200000
+CONFIG_TEXT_BASE=0x01800000
CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SYS_PROMPT="RISC-V # "
@@ -12,8 +14,6 @@ CONFIG_TARGET_AE350=y
CONFIG_RISCV_SMODE=y
# CONFIG_AVAILABLE_HARTS is not set
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index e59ba0c38a..16461e7bf9 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -1,7 +1,9 @@
CONFIG_RISCV=y
-CONFIG_TEXT_BASE=0x01200000
+CONFIG_TEXT_BASE=0x01800000
CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_SPL_TEXT_BASE=0x80000000
@@ -13,8 +15,6 @@ CONFIG_TARGET_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_SPL_XIP=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index cb69514a7e..c2793cd593 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -1,7 +1,9 @@
CONFIG_RISCV=y
-CONFIG_TEXT_BASE=0x01200000
+CONFIG_TEXT_BASE=0x01800000
CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SYS_PROMPT="RISC-V # "
@@ -13,8 +15,6 @@ CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
# CONFIG_AVAILABLE_HARTS is not set
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000
CONFIG_SYS_MONITOR_BASE=0x88000000
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index e0773fa0aa..bdc09d035d 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -1,7 +1,9 @@
CONFIG_RISCV=y
-CONFIG_TEXT_BASE=0x01200000
+CONFIG_TEXT_BASE=0x01800000
CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_SPL_TEXT_BASE=0x80000000
@@ -14,8 +16,6 @@ CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_SPL_XIP=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000
CONFIG_SYS_MONITOR_BASE=0x88000000
--
2.38.0.68.ge85701b4af.dirty
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] riscv: Rename Andes cpu and board names
2023-02-09 8:34 [PATCH 1/2] riscv: Rename Andes cpu and board names Leo Yu-Chi Liang
2023-02-09 8:34 ` [PATCH 2/2] riscv: ae350: Adjust the memory layout of ae350 Leo Yu-Chi Liang
@ 2023-02-12 15:57 ` Yu-Chien Peter Lin
[not found] ` <PU1PR03MB29973BA93E3E6994D7DE5959C1DD9@PU1PR03MB2997.apcprd03.prod.outlook.com>
2 siblings, 0 replies; 5+ messages in thread
From: Yu-Chien Peter Lin @ 2023-02-12 15:57 UTC (permalink / raw)
To: Leo Yu-Chi Liang; +Cc: u-boot
On Thu, Feb 09, 2023 at 04:34:13PM +0800, Leo Yu-Chi Liang wrote:
> The current ae350-related defconfigs could also
> support newer Andes CPU IP, so modify the names of CPU
> from ax25 to andesv5, and board name from ax25-ae350 to ae350.
>
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] riscv: Rename Andes cpu and board names
[not found] ` <PU1PR03MB29973BA93E3E6994D7DE5959C1DD9@PU1PR03MB2997.apcprd03.prod.outlook.com>
@ 2023-02-13 8:20 ` Rick Chen
0 siblings, 0 replies; 5+ messages in thread
From: Rick Chen @ 2023-02-13 8:20 UTC (permalink / raw)
To: Leo Liang; +Cc: U-Boot Mailing List, peterlin, rick
> From: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>
> Sent: Thursday, February 09, 2023 4:34 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>
> Subject: [PATCH 1/2] riscv: Rename Andes cpu and board names
>
> The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350.
>
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] riscv: ae350: Adjust the memory layout of ae350
[not found] ` <PU1PR03MB299707FBC7804F51D8384466C1DD9@PU1PR03MB2997.apcprd03.prod.outlook.com>
@ 2023-02-13 8:27 ` Rick Chen
0 siblings, 0 replies; 5+ messages in thread
From: Rick Chen @ 2023-02-13 8:27 UTC (permalink / raw)
To: Leo Liang; +Cc: U-Boot Mailing List, peterlin, rick
> From: Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>
> Sent: Thursday, February 09, 2023 4:34 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志) <rick@andestech.com>; Peter Yu-Chien Lin(林宇謙) <peterlin@andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang@andestech.com>
> Subject: [PATCH 2/2] riscv: ae350: Adjust the memory layout of ae350
>
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> configs/ae350_rv32_spl_defconfig | 6 +++---
> configs/ae350_rv32_spl_xip_defconfig | 6 +++---
> configs/ae350_rv64_spl_defconfig | 6 +++---
> configs/ae350_rv64_spl_xip_defconfig | 6 +++---
> 4 files changed, 12 insertions(+), 12 deletions(-)
Reviewed-by: Rick Chen <rick@andestech.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-02-13 8:28 UTC | newest]
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2023-02-09 8:34 [PATCH 1/2] riscv: Rename Andes cpu and board names Leo Yu-Chi Liang
2023-02-09 8:34 ` [PATCH 2/2] riscv: ae350: Adjust the memory layout of ae350 Leo Yu-Chi Liang
[not found] ` <PU1PR03MB299707FBC7804F51D8384466C1DD9@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-13 8:27 ` Rick Chen
2023-02-12 15:57 ` [PATCH 1/2] riscv: Rename Andes cpu and board names Yu-Chien Peter Lin
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2023-02-13 8:20 ` Rick Chen
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