From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F295C636D4 for ; Mon, 13 Feb 2023 08:47:03 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AA9B880B99; Mon, 13 Feb 2023 09:47:00 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7910D80AE6; Mon, 13 Feb 2023 09:46:58 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 77E0380AE0 for ; Mon, 13 Feb 2023 09:46:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 31D8kRkr083531; Mon, 13 Feb 2023 16:46:27 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 13 Feb 2023 16:46:26 +0800 Date: Mon, 13 Feb 2023 08:46:11 +0000 From: Leo Liang To: Xiang W CC: David Abdurachmanov , , , , , , Subject: Re: [PATCH v2] riscv: cancel the limitation that NR_CPUS is less than or equal to 32 Message-ID: References: <20211221233253.123268-1-wxjstz@126.com> <20211229092310.GA1314619@atcsi01> <3e3ee6841f15a8c1a8608098e3dd024d22dbe0d7.camel@126.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3e3ee6841f15a8c1a8608098e3dd024d22dbe0d7.camel@126.com> User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 31D8kRkr083531 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Xiang, On Sat, Feb 11, 2023 at 10:11:31PM +0800, Xiang W wrote: > 在 2023-02-10星期五的 07:25 +0000，Leo Liang写道： > > Hi Xiang, > > > > On Fri, Feb 03, 2023 at 03:24:37PM +0100, David Abdurachmanov wrote: > > > On Mon, Jan 3, 2022 at 1:13 PM Leo Liang wrote: > > > > > > > > On Thu, Dec 30, 2021 at 01:55:15AM +0800, Xiang W wrote: > > > > > 在 2021-12-29星期三的 17:23 +0800，Leo Liang写道： > > > > > > Hi Xiang, > > > > > > On Wed, Dec 22, 2021 at 07:32:53AM +0800, Xiang W wrote: > > > > > > > Various specifications of riscv allow the number of hart to be > > > > > > > greater than 32. The limit of 32 is determined by > > > > > > > gd->arch.available_harts. We can eliminate this limitation through > > > > > > > bitmaps. Currently, the number of hart is limited to 4095, and 4095 > > > > > > > is the limit of the RISC-V Advanced Core Local Interruptor > > > > > > > Specification. > > > > > > > > > > > > > > Test on sifive unmatched. > > > > > > > > > > > > > > Signed-off-by: Xiang W > > > > > > > --- > > > > > > > Changes since v1: > > > > > > > > > > > > > > * When NR_CPUS is very large, the value of GD_AVAILABLE_HARTS will > > > > > > >   overflow the immediate range of ld/lw. This patch fixes this > > > > > > >   problem > > > > > > > > > > > > > >  arch/riscv/Kconfig                   |  4 ++-- > > > > > > >  arch/riscv/cpu/start.S               | 21 ++++++++++++++++----- > > > > > > >  arch/riscv/include/asm/global_data.h |  4 +++- > > > > > > >  arch/riscv/lib/smp.c                 |  2 +- > > > > > > >  4 files changed, 22 insertions(+), 9 deletions(-) > > > > > > > > > > > > > I noticed that this has never landed in U-Boot. Was this forgotten or > > > dropped for some reason (couldn't find anything)? > > > > > > The current limit on the Linux kernel side is 512. The default on > > > 64-bit (riscv64) is 64. > > > > > > david > > > > The patch seems to cause some CI error (timeout on QEMU). > > (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15076) > > Could you take a look at it if you have time? > > > > Best regards, > > Leo > > sorry! I missing a bug. There is an error in calculating the starting address > of available_harts. The patch for start.S needs to be updated. > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S > index 76850ec9be..92f3b78f29 100644 > --- a/arch/riscv/cpu/start.S > +++ b/arch/riscv/cpu/start.S > @@ -166,11 +166,22 @@ wait_for_gd_init: > mv gp, s0 > > /* register available harts in the available_harts mask */ > - li t1, 1 > - sll t1, t1, tp > - LREG t2, GD_AVAILABLE_HARTS(gp) > - or t2, t2, t1 > - SREG t2, GD_AVAILABLE_HARTS(gp) > + li t1, GD_AVAILABLE_HARTS > + add t1, t1, gp > +#if defined(CONFIG_ARCH_RV64I) > + srli t2, tp, 6 > + slli t2, t2, 3 > +#elif defined(CONFIG_ARCH_RV32I) > + srli t2, tp, 5 > + slli t2, t2, 2 > +#endif > + add t1, t1, t2 > + LREG t2, 0(t1) > + li t3, 1 > + sll t3, t3, tp > + or t2, t2, t3 > + SREG t2, 0(t1) > > amoswap.w.rl zero, zero, 0(t0) > > The mailing list cannot receive my mail, please help to update > I have updated the patch. (https://patchwork.ozlabs.org/project/uboot/patch/20230213084313.10419-1-ycliang@andestech.com/) Could you take a look to see if there is any issue? Best regards, Leo