From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9B16C05027 for ; Mon, 13 Feb 2023 03:06:54 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 57C5485103; Mon, 13 Feb 2023 04:06:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 6677084528; Mon, 13 Feb 2023 04:06:48 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 84DBF82A24 for ; Mon, 13 Feb 2023 04:06:44 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=peterlin@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 31D36WUR029894; Mon, 13 Feb 2023 11:06:32 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from APC323 (10.0.12.98) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 13 Feb 2023 11:06:31 +0800 Date: Mon, 13 Feb 2023 11:01:46 +0000 From: Yu-Chien Peter Lin To: Simon Glass CC: , , Subject: Re: [RFC PATCH] doc: arch: Add document for RISC-V architecture Message-ID: References: <20230212070053.14800-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.9 (2022-11-12) X-Originating-IP: [10.0.12.98] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 31D36WUR029894 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Sun, Feb 12, 2023 at 12:25:56PM -0700, Simon Glass wrote: > On Sun, 12 Feb 2023 at 00:01, Yu Chien Peter Lin wrote: > > > > This patch adds a brief introduction to the RISC-V architecture and > > the typical boot process used on a variety of RISC-V platforms. > > > > Signed-off-by: Yu Chien Peter Lin > > --- > > Hi RISC-V community, > > > > Please leave a comment if there is anything I've missed that should > > be mentioned in the document. Thanks. > > --- > > doc/arch/index.rst | 1 + > > doc/arch/riscv.rst | 43 +++++++++++++++++++++++++++++++++++++++++++ > > 2 files changed, 44 insertions(+) > > create mode 100644 doc/arch/riscv.rst > > Reviewed-by: Simon Glass > > Looks good. One nit is that we try to talk in terms of boot 'phases' > rather than stages. Hi Simon, Thanks for the review, I'll update in the next patch. Best regards, Peter Lin > Regards, > Simon