From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9481C636CC for ; Tue, 14 Feb 2023 03:33:55 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 96AD185805; Tue, 14 Feb 2023 04:33:53 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 5A5C98580E; Tue, 14 Feb 2023 04:33:52 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 556CF857E0 for ; Tue, 14 Feb 2023 04:33:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=peterlin@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 31E3Xcs1093956; Tue, 14 Feb 2023 11:33:38 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from APC323 (10.0.12.98) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Tue, 14 Feb 2023 11:33:37 +0800 Date: Tue, 14 Feb 2023 11:28:46 +0000 From: Yu-Chien Peter Lin To: Heinrich Schuchardt CC: , , , Subject: Re: [RFC PATCH] doc: arch: Add document for RISC-V architecture Message-ID: References: <20230212070053.14800-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.9 (2022-11-12) X-Originating-IP: [10.0.12.98] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 31E3Xcs1093956 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Heinrich, On Mon, Feb 13, 2023 at 08:36:30AM +0100, Heinrich Schuchardt wrote: > On 2/12/23 08:00, Yu Chien Peter Lin wrote: > > This patch adds a brief introduction to the RISC-V architecture and > > the typical boot process used on a variety of RISC-V platforms. > > > > Signed-off-by: Yu Chien Peter Lin > > --- > > Hi RISC-V community, > > > > Please leave a comment if there is anything I've missed that should > > be mentioned in the document. Thanks. > > --- > > doc/arch/index.rst | 1 + > > doc/arch/riscv.rst | 43 +++++++++++++++++++++++++++++++++++++++++++ > > 2 files changed, 44 insertions(+) > > create mode 100644 doc/arch/riscv.rst > > > > diff --git a/doc/arch/index.rst b/doc/arch/index.rst > > index b3e85f9bf3..b8da4b8c8e 100644 > > --- a/doc/arch/index.rst > > +++ b/doc/arch/index.rst > > @@ -11,6 +11,7 @@ Architecture-specific doc > > m68k > > mips > > nios2 > > + riscv > > sandbox/index > > sh > > x86 > > diff --git a/doc/arch/riscv.rst b/doc/arch/riscv.rst > > new file mode 100644 > > index 0000000000..243e7e7e2e > > --- /dev/null > > +++ b/doc/arch/riscv.rst > > @@ -0,0 +1,43 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > +.. Copyright (C) 2023, Yu Chien Peter Lin > > + > > +RISC-V > > +====== > > + > > +Overview > > +-------- > > + > > +This document outlines the U-Boot boot process for the RISC-V architecture. > > +RISC-V is an open-source instruction set architecture (ISA) based on the > > +principles of reduced instruction set computing (RISC). It has been designed > > +to be flexible and customizable, allowing it to be adapted to different use > > +cases, from embedded systems to high performance servers. > > + > > +Typical Boot Process > > +-------------------- > > + > > +RISC-V production boot images typically include a U-Boot SPL for platform-specific > > %s/typically include/may include/ > > Many boards don't use SPL: > > ae350_rv32_defconfig > ae350_rv64_defconfig > sipeed_maix_bitm_defconfig > sipeed_maix_smode_defconfig > openpiton_riscv64_defconfig > qemu-riscv64_defconfig > > Please provide a description of those boot processes too. Sure, I will add a description for these defconfigs. > > +initialization. The U-Boot SPL then loads a FIT image (u-boot.itb), which contains > > +an SBI (Supervisor Binary Interface) firmware such as `OpenSBI `_, as well as a regular > > Please, try to stay within 80 columns. OK, will fix. > %s/an SBI (Supervisor Binary Interface) firmware/a firmware providing > the SBI (Supervisor Binary Interface)/ OK. > > +U-Boot (or U-Boot proper) running in S-mode. Finally, the S-mode Operating System > > +is loaded. > > + > > +In between the boot stages, the hartid is passed through the a0 register, and the > > +start address of the devicetree is passed through the a1 register. > > + > > +The following diagram illustrates the boot process:: > > + > > + <----------( M-mode )--------><-------( S-mode )------> > > + +------------+ +---------+ +--------+ +--------+ > > + | U-Boot SPL |-->| SBI |--->| U-Boot |-->| OS | > > + +------------+ +---------+ +--------+ +--------+ > > SBI (Supervisory Binary Interface) is an interface not a software. So it > does not fit into this diagram. Sure, I will rename the block to SBI firmware. > Best regards > > Heinrich > > > + > > +To examine the boot process with the QEMU virt machine, you can follow the steps > > +in the following document: > > +:doc:`../board/emulation/qemu-riscv.rst` > > + > > +Toolchain > > +--------- > > + > > +You can build the `RISC-V GNU toolchain `_ from scratch, or download a > > +pre-built toolchain from the `releases page `_. >