From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 292CDC4332F for ; Wed, 12 Oct 2022 05:54:46 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E15DA84D88; Wed, 12 Oct 2022 07:54:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id B3A3384D9F; Wed, 12 Oct 2022 07:54:42 +0200 (CEST) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 51A5E84C86 for ; Wed, 12 Oct 2022 07:54:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 29C5sQO6047534; Wed, 12 Oct 2022 13:54:26 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 12 Oct 2022 13:54:22 +0800 Date: Wed, 12 Oct 2022 05:54:11 +0000 From: Leo Liang To: Heinrich Schuchardt CC: Rick Chen , Tom Rini , Subject: Re: [PATCH 1/1] riscv: support building double-float modules Message-ID: References: <20221008091757.53072-1-heinrich.schuchardt@canonical.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20221008091757.53072-1-heinrich.schuchardt@canonical.com> User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 29C5sQO6047534 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Heinrich, On Sat, Oct 08, 2022 at 11:17:57AM +0200, Heinrich Schuchardt wrote: > The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a > compiled for double-float. To link to it we have to adjust how we build > U-Boot. > > As U-Boot actually does not use floating point at all this should not > make a significant difference for the produced binaries. > > Signed-off-by: Heinrich Schuchardt > --- > arch/riscv/Kconfig | 14 ++++++++++++++ > arch/riscv/Makefile | 17 ++++++++++++++--- > 2 files changed, 28 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 32a90b83b5..8add95c8ef 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -152,6 +152,20 @@ config RISCV_ISA_C > when building U-Boot, which results in compressed instructions in the > U-Boot binary. > > +config RISCV_ISA_F > + bool "Standard extension for Single-Precision Floating Point" > + default y > + help > + Adds "F" to the ISA string passed to the compiler. > + > +config RISCV_ISA_D > + bool "Standard extension forr Double-Precision Floating Point" typo "forr" > + depends on RISCV_ISA_F > + default y > + help > + Adds "D" to the ISA string passed to the compiler and changes the > + riscv32 ABI from ilp32 to ipl32d. typo "ipl32d" I think we do not need to specify that the option is created for rv32. > + > config RISCV_ISA_A > def_bool y > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 53d1194ffb..d1b6e86dd8 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -5,15 +5,24 @@ > > ifeq ($(CONFIG_ARCH_RV64I),y) > ARCH_BASE = rv64im > - ABI = lp64 > + ABI_BASE = lp64 > endif > ifeq ($(CONFIG_ARCH_RV32I),y) > ARCH_BASE = rv32im > - ABI = ilp32 > + ABI_BASE = ilp32 > endif > ifeq ($(CONFIG_RISCV_ISA_A),y) > ARCH_A = a > endif > +ifeq ($(CONFIG_RISCV_ISA_F),y) > + ARCH_F = f > +endif > +ifeq ($(CONFIG_RISCV_ISA_D),y) > + ARCH_D = d > +ifeq ($(CONFIG_ARCH_RV32I),y) I think we do not need this if statement as Rick stated. The default libgcc.a of both rv32 and rv64 toolchains from kernel.org are built with double float abi, so this CONFIG_RISCV_ISA_D could be applied to rv64 setup as well. Other than the above, Looks good to me. Reviewed-by: Leo Yu-Chi Liang > + ABI_D = d > +endif > +endif > ifeq ($(CONFIG_RISCV_ISA_C),y) > ARCH_C = c > endif > @@ -24,7 +33,9 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) > CMODEL = medany > endif > > -RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) > + > +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) > +ABI = $(ABI_BASE)$(ABI_D) > > # Newer binutils versions default to ISA spec version 20191213 which moves some > # instructions from the I extension to the Zicsr and Zifencei extensions. > -- > 2.37.2 > Thanks for catching rv32 compilation issue. Best regards, Leo