From: Conor Dooley <conor@kernel.org>
To: Padmarao Begari <padmarao.begari@microchip.com>
Cc: u-boot@lists.denx.de, jagan@amarulasolutions.com,
rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com,
cyril.jean@microchip.com, conor.dooley@microchip.com,
valentina.fernandezalanis@microchip.com,
nagasuresh.relli@microchip.com
Subject: Re: [PATCH 2/4] riscv: dts: Add QSPI NAND device node
Date: Wed, 19 Oct 2022 16:59:21 +0100 [thread overview]
Message-ID: <Y1Ae2fDZcVMHYn+c@spud> (raw)
In-Reply-To: <20221019145322.2274420-3-padmarao.begari@microchip.com>
On Wed, Oct 19, 2022 at 08:23:20PM +0530, Padmarao Begari wrote:
> riscv: dts: Add QSPI NAND device node
I didn't notice this on 1/3, but I think we need to mention which board
that this is being added for in the shortlog.
Thanks,
Conor.
> Add QSPI NAND device node to the Microchip PolarFire SoC
> Icicle kit device tree
>
> Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
> ---
> arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> index 876c475069..679221e13f 100644
> --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> @@ -18,6 +18,7 @@
> aliases {
> serial1 = &uart1;
> ethernet0 = &mac1;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -113,3 +114,17 @@
> ti,fifo-depth = <0x1>;
> };
> };
> +
> +&qspi {
> + status = "okay";
> + num-cs = <1>;
> + flash0: spi-nand@0 {
> + compatible = "spi-nand";
> + reg = <0x0>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + spi-max-frequency = <20000000>;
> + spi-cpol;
> + spi-cpha;
> + };
> +};
> --
> 2.25.1
>
next prev parent reply other threads:[~2022-10-19 15:59 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-19 14:53 [PATCH 0/4] Update Microchip PolarFire SoC Padmarao Begari
2022-10-19 14:53 ` [PATCH 1/4] riscv: dts: update memory configuration Padmarao Begari
2022-10-19 15:57 ` Conor Dooley
2022-10-20 5:20 ` Padmarao.Begari
2022-10-19 14:53 ` [PATCH 2/4] riscv: dts: Add QSPI NAND device node Padmarao Begari
2022-10-19 15:28 ` Tudor.Ambarus
2022-10-20 5:22 ` Padmarao.Begari
2022-10-19 15:59 ` Conor Dooley [this message]
2022-10-20 5:24 ` Padmarao.Begari
2022-10-19 14:53 ` [PATCH 3/4] riscv: Update Microchip MPFS Icicle Kit support Padmarao Begari
2022-10-19 16:09 ` Conor Dooley
2022-10-19 14:53 ` [PATCH 4/4] spi: Add Microchip PolarFire SoC QSPI driver Padmarao Begari
2022-10-19 15:16 ` Tudor.Ambarus
2022-10-19 15:47 ` Conor Dooley
2022-10-20 5:27 ` Padmarao.Begari
2022-10-19 16:20 ` Conor Dooley
2022-10-20 5:28 ` Padmarao.Begari
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Y1Ae2fDZcVMHYn+c@spud \
--to=conor@kernel.org \
--cc=bmeng.cn@gmail.com \
--cc=conor.dooley@microchip.com \
--cc=cyril.jean@microchip.com \
--cc=jagan@amarulasolutions.com \
--cc=nagasuresh.relli@microchip.com \
--cc=padmarao.begari@microchip.com \
--cc=rick@andestech.com \
--cc=u-boot@lists.denx.de \
--cc=valentina.fernandezalanis@microchip.com \
--cc=ycliang@andestech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox