From: Conor Dooley <conor@kernel.org>
To: Padmarao Begari <padmarao.begari@microchip.com>
Cc: u-boot@lists.denx.de, jagan@amarulasolutions.com,
rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com,
cyril.jean@microchip.com, conor.dooley@microchip.com,
valentina.fernandezalanis@microchip.com,
nagasuresh.relli@microchip.com
Subject: Re: [PATCH 4/4] spi: Add Microchip PolarFire SoC QSPI driver
Date: Wed, 19 Oct 2022 17:20:30 +0100 [thread overview]
Message-ID: <Y1AjznnDEMUYMXkO@spud> (raw)
In-Reply-To: <20221019145322.2274420-5-padmarao.begari@microchip.com>
On Wed, Oct 19, 2022 at 08:23:22PM +0530, Padmarao Begari wrote:
> Add QSPI driver code for the Microchip PolarFire SoC.
> This driver supports the qspi standard, dual and quad
> mode interfaces.
>
> Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
> Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
> ---
> drivers/spi/Kconfig | 6 +
> drivers/spi/Makefile | 1 +
> drivers/spi/microchip_qspi.c | 504 +++++++++++++++++++++++++++++++++++
> 3 files changed, 511 insertions(+)
> create mode 100644 drivers/spi/microchip_qspi.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 2f12081f88..690306309a 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -237,6 +237,12 @@ config MESON_SPIFC
> This driver can be used to access the SPI NOR flash chips on
> Amlogic Meson SoCs.
>
> +config MICROCHIP_QSPI
Can this be MICROCHIP_COREQSPI to match my proposed name of the driver
and the function/structure names in the driver?
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> +
> +static const struct udevice_id mchp_coreqspi_ids[] = {
> + { .compatible = "microchip,mpfs-qspi" },
Could we add microchip,coreqspi-rtl-v2 to the compatible list here
please to match the linux driver? The linux driver works perfectly well
with the fabric core and I assume that's the case for the the U-Boot
driver too?
Thanks,
Conor.
> + { }
> +};
> +
> +U_BOOT_DRIVER(mchp_coreqspi) = {
> + .name = "mchp_coreqspi",
> + .id = UCLASS_SPI,
> + .of_match = mchp_coreqspi_ids,
> + .ops = &mchp_coreqspi_ops,
> + .priv_auto = sizeof(struct mchp_coreqspi),
> + .probe = mchp_coreqspi_probe,
> +};
> --
> 2.25.1
>
next prev parent reply other threads:[~2022-10-19 16:20 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-19 14:53 [PATCH 0/4] Update Microchip PolarFire SoC Padmarao Begari
2022-10-19 14:53 ` [PATCH 1/4] riscv: dts: update memory configuration Padmarao Begari
2022-10-19 15:57 ` Conor Dooley
2022-10-20 5:20 ` Padmarao.Begari
2022-10-19 14:53 ` [PATCH 2/4] riscv: dts: Add QSPI NAND device node Padmarao Begari
2022-10-19 15:28 ` Tudor.Ambarus
2022-10-20 5:22 ` Padmarao.Begari
2022-10-19 15:59 ` Conor Dooley
2022-10-20 5:24 ` Padmarao.Begari
2022-10-19 14:53 ` [PATCH 3/4] riscv: Update Microchip MPFS Icicle Kit support Padmarao Begari
2022-10-19 16:09 ` Conor Dooley
2022-10-19 14:53 ` [PATCH 4/4] spi: Add Microchip PolarFire SoC QSPI driver Padmarao Begari
2022-10-19 15:16 ` Tudor.Ambarus
2022-10-19 15:47 ` Conor Dooley
2022-10-20 5:27 ` Padmarao.Begari
2022-10-19 16:20 ` Conor Dooley [this message]
2022-10-20 5:28 ` Padmarao.Begari
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