From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 679B7C433FE for ; Sat, 22 Oct 2022 11:21:51 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A172084F39; Sat, 22 Oct 2022 13:21:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="SM9rc3mq"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8B38984F45; Sat, 22 Oct 2022 13:21:46 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 31C4284F11 for ; Sat, 22 Oct 2022 13:21:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=conor@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 28BBE60CA4; Sat, 22 Oct 2022 11:21:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A401C433D7; Sat, 22 Oct 2022 11:21:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666437700; bh=MEtjbkj7OSjheB1LadlraYfryqNuLbgx9XtvkoRPTcU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=SM9rc3mqL19B4HvikYMJq45h1d9lt5iv1LksAATVIOr4YdgIrq6ShskfXnTd8WFUV 1HI2g9IBGhKUCcum9wswHBO+FhbA+byc91NbiuQE36TnCAHCxPMx3aW2bEl5et4JrA /udPn1b8wKi6AeH7Uj2t4jUWlM4WbkSbgCzdmk039yCFdI2B7LCrPmJFwLTp86Lew9 ic6jQaHmwUSINzW+PQgnjyWI1Np/zHcI0WJ2/mGsuTn80hsdmY/rrFG7q7XbOBjVF9 FNrasoh1OLUrO9B5QqsdBmnFlzKb56K5SwyOrrdTvwADL1rE39MjN66nbc9tG1Pzoy NfDUtVbScVpqw== Date: Sat, 22 Oct 2022 12:21:35 +0100 From: Conor Dooley To: Padmarao Begari Cc: u-boot@lists.denx.de, jagan@amarulasolutions.com, rick@andestech.com, ycliang@andestech.com, bmeng.cn@gmail.com, cyril.jean@microchip.com, conor.dooley@microchip.com, valentina.fernandezalanis@microchip.com, nagasuresh.relli@microchip.com Subject: Re: [PATCH v2 1/4] riscv: dts: Update memory configuration Message-ID: References: <20221021065922.2327875-1-padmarao.begari@microchip.com> <20221021065922.2327875-2-padmarao.begari@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221021065922.2327875-2-padmarao.begari@microchip.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote: > In the v2022.10 Icicle reference design, the seg registers are going to be Hey Padmarao, Since the release was done the other day I think that this should be s/are going to be/have been > changed, resulting in a required change to the memory map. > A small 4MB reservation is made at the end of 32-bit DDR to provide some > memory for the HSS to use, so that it can cache its payload between > reboots of a specific context. > > Co-developed-by: Conor Dooley > Signed-off-by: Conor Dooley > Signed-off-by: Padmarao Begari > Reviewed-by: Conor Dooley > --- > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70 ++++---------------- > 1 file changed, 14 insertions(+), 56 deletions(-) > > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts > index 287ef3d23b..876c475069 100644 > --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: (GPL-2.0+ OR MIT) > /* > - * Copyright (C) 2021 Microchip Technology Inc. > + * Copyright (C) 2021-2022 Microchip Technology Inc. > * Padmarao Begari > */ > > @@ -28,70 +28,28 @@ > timebase-frequency = ; > }; FWIW I think we should add the compatible that the linux dt has, signifying that this memory layout is compatible with the v2022.10 release and later (w/ appropriate line-wrapping ofc): compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", "microchip,mpfs"; Other than that: Reviewed-by: Conor Dooley > > - reserved-memory { > - ranges; > - #size-cells = <2>; > - #address-cells = <2>; > - > - fabricbuf0: fabricbuf@0 { > - compatible = "shared-dma-pool"; > - reg = <0x0 0xae000000 0x0 0x2000000>; > - label = "fabricbuf0-ddr-c"; > - }; > - > - fabricbuf1: fabricbuf@1 { > - compatible = "shared-dma-pool"; > - reg = <0x0 0xc0000000 0x0 0x8000000>; > - label = "fabricbuf1-ddr-nc"; > - }; > - > - fabricbuf2: fabricbuf@2 { > - compatible = "shared-dma-pool"; > - reg = <0x0 0xd8000000 0x0 0x8000000>; > - label = "fabricbuf2-ddr-nc-wcb"; > - }; > - }; > - > - udmabuf0 { > - compatible = "ikwzm,u-dma-buf"; > - device-name = "udmabuf-ddr-c0"; > - minor-number = <0>; > - size = <0x0 0x2000000>; > - memory-region = <&fabricbuf0>; > - sync-mode = <3>; > - }; > - > - udmabuf1 { > - compatible = "ikwzm,u-dma-buf"; > - device-name = "udmabuf-ddr-nc0"; > - minor-number = <1>; > - size = <0x0 0x8000000>; > - memory-region = <&fabricbuf1>; > - sync-mode = <3>; > - }; > - > - udmabuf2 { > - compatible = "ikwzm,u-dma-buf"; > - device-name = "udmabuf-ddr-nc-wcb0"; > - minor-number = <2>; > - size = <0x0 0x8000000>; > - memory-region = <&fabricbuf2>; > - sync-mode = <3>; > - }; > - > ddrc_cache_lo: memory@80000000 { > device_type = "memory"; > - reg = <0x0 0x80000000 0x0 0x2e000000>; > - clocks = <&clkcfg CLK_DDRC>; > + reg = <0x0 0x80000000 0x0 0x40000000>; > status = "okay"; > }; > > ddrc_cache_hi: memory@1000000000 { > device_type = "memory"; > - reg = <0x10 0x0 0x0 0x40000000>; > - clocks = <&clkcfg CLK_DDRC>; > + reg = <0x10 0x40000000 0x0 0x40000000>; > status = "okay"; > }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + hss_payload: region@BFC00000 { > + reg = <0x0 0xBFC00000 0x0 0x400000>; > + no-map; > + }; > + }; > }; > > &uart1 { > -- > 2.25.1 >