From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E561C433FE for ; Wed, 2 Nov 2022 11:21:22 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 31EE085082; Wed, 2 Nov 2022 12:21:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A3D0285084; Wed, 2 Nov 2022 12:21:18 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 110C085038 for ; Wed, 2 Nov 2022 12:21:15 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 2A2BL67g002796; Wed, 2 Nov 2022 19:21:06 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 2 Nov 2022 19:21:04 +0800 Date: Wed, 2 Nov 2022 11:21:03 +0000 From: Leo Liang To: Conor Dooley CC: Rick Chen , Lukasz Majewski , "Sean Anderson" , Padmarao Begari , Subject: Re: [PATCH v1 3/6] clk: microchip: mpfs: fix reference clock handling Message-ID: References: <20221025075848.110754-1-conor.dooley@microchip.com> <20221025075848.110754-4-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20221025075848.110754-4-conor.dooley@microchip.com> User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 2A2BL67g002796 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Tue, Oct 25, 2022 at 08:58:46AM +0100, Conor Dooley wrote: > The original devicetrees for PolarFire SoC messed up & defined the > msspll's output as a fixed-frequency, 600 MHz clock & used that as the > input for the clock controller node. The msspll is not a fixed > frequency clock and later devicetrees handled this properly. Check the > devicetree & if it is one of the fixed ones, register the msspll. > Otherwise, skip registering it & pass the reference clock directly to > the cfg clock registration function so that existing devicetrees are > not broken by this change. > > As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for > it, based on the one in Linux. > > Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") > Signed-off-by: Conor Dooley > --- > drivers/clk/microchip/mpfs_clk.c | 23 ++++- > drivers/clk/microchip/mpfs_clk.h | 8 ++ > drivers/clk/microchip/mpfs_clk_msspll.c | 119 ++++++++++++++++++++++++ > 3 files changed, 149 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/microchip/mpfs_clk_msspll.c Reviewed-by: Leo Yu-Chi Liang