From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D07ECC4332F for ; Wed, 2 Nov 2022 11:21:57 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1FAF185090; Wed, 2 Nov 2022 12:21:55 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 869EA8508B; Wed, 2 Nov 2022 12:21:53 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 17E2284F66 for ; Wed, 2 Nov 2022 12:21:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 2A2BLgkZ002865; Wed, 2 Nov 2022 19:21:42 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 2 Nov 2022 19:21:42 +0800 Date: Wed, 2 Nov 2022 11:21:40 +0000 From: Leo Liang To: Conor Dooley CC: Rick Chen , Lukasz Majewski , "Sean Anderson" , Padmarao Begari , Subject: Re: [PATCH v1 4/6] clk: microchip: mpfs: fix periph clk parentage Message-ID: References: <20221025075848.110754-1-conor.dooley@microchip.com> <20221025075848.110754-5-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20221025075848.110754-5-conor.dooley@microchip.com> User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 2A2BLgkZ002865 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Tue, Oct 25, 2022 at 08:58:47AM +0100, Conor Dooley wrote: > Not all "periph" clocks are children of the AHB clock, some have the AXI > clock as their parent & the mtimer clock is derived from the external > reference clock directly. Stop assuming the AHB clock to be the parent > of all "periph" clocks and define their correct parents instead. > > Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") > Signed-off-by: Conor Dooley > --- > drivers/clk/microchip/mpfs_clk.c | 4 +- > drivers/clk/microchip/mpfs_clk.h | 4 +- > drivers/clk/microchip/mpfs_clk_periph.c | 72 +++++++++++++------------ > 3 files changed, 42 insertions(+), 38 deletions(-) Reviewed-by: Leo Yu-Chi Liang