From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 004D8C4332F for ; Wed, 2 Nov 2022 11:23:12 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 64F6985093; Wed, 2 Nov 2022 12:23:10 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id B8A1B85094; Wed, 2 Nov 2022 12:23:08 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3EA8B85091 for ; Wed, 2 Nov 2022 12:23:06 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 2A2BMrkd003386; Wed, 2 Nov 2022 19:22:53 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 2 Nov 2022 19:22:49 +0800 Date: Wed, 2 Nov 2022 11:22:47 +0000 From: Leo Liang To: Conor Dooley CC: Rick Chen , Lukasz Majewski , "Sean Anderson" , Padmarao Begari , Subject: Re: [PATCH v1 6/6] riscv: dts: fix the mpfs's reference clock frequency Message-ID: References: <20221025075848.110754-1-conor.dooley@microchip.com> <20221025075848.110754-7-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20221025075848.110754-7-conor.dooley@microchip.com> User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 2A2BMrkd003386 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Tue, Oct 25, 2022 at 08:58:49AM +0100, Conor Dooley wrote: > The initial devicetree for PolarFire SoC incorrectly created a fixed > frequency clock in the devicetree to represent the msspll, but the > msspll is not a fixed frequency clock. The actual reference clock on a > board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit. > Swap the incorrect representation of the msspll out for the actual > reference clock. > > Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit") > Signed-off-by: Conor Dooley > --- > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 ++++ > arch/riscv/dts/microchip-mpfs.dtsi | 14 ++++++-------- > 2 files changed, 10 insertions(+), 8 deletions(-) Reviewed-by: Leo Yu-Chi Liang