From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC559C4332F for ; Fri, 2 Dec 2022 08:46:32 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6541E851D4; Fri, 2 Dec 2022 09:46:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 6F36C8526B; Fri, 2 Dec 2022 09:46:29 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C7A268511E for ; Fri, 2 Dec 2022 09:46:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 2B28kHCx066706; Fri, 2 Dec 2022 16:46:17 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 2 Dec 2022 16:46:13 +0800 Date: Fri, 2 Dec 2022 08:46:08 +0000 From: Leo Liang To: Kautuk Consul CC: Bin Meng , Rick Chen , , , Subject: Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot Message-ID: References: <20220923070320.617623-1-kconsul@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 2B28kHCx066706 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Kautuk, Sorry for the late reply. The CI failure still exists and if tested on QEMU(7.0.0) without a gdb attached, it is possible that we get weird output on console.[1] Another thing is that with your patch, QEMU could not exit with Ctrl a + x. This might be the reason for CI failure (timeout). Could you take a look at this? Yet with a gdb attached, everything works as expected, So maybe we could disable semihosting as default? Best regards, Leo [1] The weird console output looks like below, it outputs random character without us typing anything. U-Boot 2022.10-rc5 (Dec 02 2022 - 16:27:43 +0800) CPU: rv64imafdcsuh Model: riscv-virtio,qemu DRAM: 2 GiB Core: 35 devices, 15 uclasses, devicetree: board Flash: 32 MiB Loading Environment from nowhere... OK In: serial_semihosting Out: serial_semihosting Err: serial_semihosting Net: eth0: virtio-net#1 Hit any key to stop autoboot: 0 => 55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 55555555555555555555555555555555555555555555555555555555555555555555 On Tue, Nov 29, 2022 at 12:27:51PM +0530, Kautuk Consul wrote: > I have tested it both on Qemu and Ventana's internal simulator. > > On Tue, Nov 29, 2022 at 12:06 PM Bin Meng wrote: > > > Hi Kautuk, > > > > On Tue, Nov 29, 2022 at 2:29 PM Kautuk Consul > > wrote: > > > > > > Hi, > > > > > > Can someone pick this patchset up ? > > > > > > It has been reviewed and there has been no comment on this in recent > > days. > > > > > > Thanks. > > > > > > On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul > > wrote: > > >> > > >> Semihosting is a mechanism that enables code running on > > >> a target to communicate and use the Input/Output > > >> facilities on a host computer that is running a debugger. > > >> This patchset adds support for semihosting in u-boot > > >> for RISCV64 targets. > > >> > > >> CHANGES since v4: > > >> - Check arch dependencies for SEMIHOSTING as well as > > SPL_SEMIHOSTING > > >> config options as per Sean's comment. > > >> - arch/riscv/lib/interrupts.c: Check for post and pre instructions > > >> of the ebreak statement whether they are as per the RISCV > > >> semihosting specification. Only then do a disable_semihosting > > >> and epc += 4 and return. > > >> > > >> Compilation and test commands for SPL and S-mode configurations > > >> ================================================================= > > >> > > >> U-Boot S-mode on QEMU virt > > >> ---------------------------- > > >> // Compilation of S-mode u-boot > > >> ARCH=riscv > > >> CROSS_COMPILE=riscv64-unknown-linux-gnu- > > >> make qemu-riscv64_smode_defconfig > > >> make > > >> // Run riscv 64-bit u-boot with opensbi on qemu > > >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ > > >> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\ > > >> u-boot/u-boot.bin > > >> > > >> U-Boot SPL on QEMU virt > > >> ------------------------ > > >> // Compilation of u-boot-spl > > >> ARCH=riscv > > >> CROSS_COMPILE=riscv64-unknown-linux-gnu- > > >> make qemu-riscv64_spl_defconfig > > >> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin > > >> // Run 64-bit u-boot-spl in qemu > > >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ > > >> u-boot/spl/u-boot-spl.bin -device\ > > >> loader,file=u-boot/u-boot.itb,addr=0x80200000 > > >> > > > > Do you have instructions on how to actually test semihosting? Does it > > require a JTAG debugger? But I see you are using QEMU? > > > > Regards, > > Bin > >