From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F65AC004D4 for ; Thu, 19 Jan 2023 18:31:07 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 787D484FB4; Thu, 19 Jan 2023 19:31:04 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="GIySV45G"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AA1C682161; Thu, 19 Jan 2023 19:31:02 +0100 (CET) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 907D88566D for ; Thu, 19 Jan 2023 19:30:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=conor@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C447861D01; Thu, 19 Jan 2023 18:30:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E381C433EF; Thu, 19 Jan 2023 18:30:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674153056; bh=vhYMGrEwlaT6/5+cKBrogwDgzOpOrKRnAeWK0U1S9G0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=GIySV45GRRkR19ZjhSSACpagcwpCVhr18/+XQtm62pybimkKwpq2z5PPHmGrmHeb0 kdfuu4dOGBOURkpP4tchf4gFXzLTmShUIgioro0w5DjZcQZ3gyBt0DmSQk5lkI1A1R AfQ/oMIsHWPwC8x9UYl5DY4EzRZNNpFgO6NwbNgn6FWAnTI1jA6c/EGPmjwEeZKpKB lu8A+6KewfGy27vwdO3tZYo0hGfTa7y1dRWrqCR4yzjWj25TXDxp91nC0pGUbqYEq8 eE9LSaa6/6KZYjPx3g9wcjmsaYkeAdvcOs9eNf8T6/W+wFeJqYss/rTXwUKurPeWZ+ bbucbu9R+H5kA== Date: Thu, 19 Jan 2023 18:30:51 +0000 From: Conor Dooley To: Sean Anderson Cc: David Abdurachmanov , Yanhong Wang , u-boot@lists.denx.de, Rick Chen , Leo , Lukasz Majewski , Lee Kuan Lim , Jianlong Huang , Emil Renner Berthing Subject: Re: [PATCH v2 14/17] riscv: dts: jh7110: Add initial StarFive JH7110 device tree Message-ID: References: <20230118081132.31403-1-yanhong.wang@starfivetech.com> <20230118081132.31403-15-yanhong.wang@starfivetech.com> <022f9da1-75db-40e9-2823-dbbf1cb6f3f5@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="7OlOoqXBjtnjUGFe" Content-Disposition: inline In-Reply-To: <022f9da1-75db-40e9-2823-dbbf1cb6f3f5@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean --7OlOoqXBjtnjUGFe Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hey Se=E1n, David, On Thu, Jan 19, 2023 at 01:26:52AM -0500, Sean Anderson wrote: > On 1/19/23 01:18, David Abdurachmanov wrote: > > On Wed, Jan 18, 2023 at 10:19 AM Yanhong Wang > > wrote: > > > + U74_4: cpu@4 { > > > + compatible =3D "sifive,u74-mc", "riscv"; > > > + reg =3D <4>; > > > + d-cache-block-size =3D <64>; > > > + d-cache-sets =3D <64>; > > > + d-cache-size =3D <32768>; > > > + d-tlb-sets =3D <1>; > > > + d-tlb-size =3D <40>; > > > + device_type =3D "cpu"; > > > + i-cache-block-size =3D <64>; > > > + i-cache-sets =3D <64>; > > > + i-cache-size =3D <32768>; > > > + i-tlb-sets =3D <1>; > > > + i-tlb-size =3D <40>; > > > + mmu-type =3D "riscv,sv39"; > > > + next-level-cache =3D <&ccache>; > > > + riscv,isa =3D "rv64imafdcbsu"; > >=20 > > Looking at SiFive U74 manuals, shouldn't this be RV64GC_Zba_Zbb_Sscofpm= f? > > U74 only supports Zba and Zbb bit manip extensions. > > This is from the 21G3.02.00 release manual. > >=20 > > Looking more, S76 core is listed in the manual as supporting up to: > > RV64IMAC_Zicsr_Zifencei_Zba_Zbb_Sscofpmf. > >=20 > > I almost forgot about _Zicsr_Zifencei (which are part of G). Shouldn't > > those be listed too in riscv,isa? AFAIU, Linux just assumes them since they weren't their own thing prior to ISA spec 20191213. I think in- & ex- cluding them are both valid... Yeah. > AFAIK we don't support Z/X in U-Boot. Does the U-Boot ISA string parsing not just ignore un-implemented extensions? If it does ignore things you don't implement, then I think including the Z extensions should be no harm. IMO, it'd be nice to have this string match whatever the hardware can support so that same Devicetree can be used for U-Boot & whatever OS it is booting. That said, I'm yet to be sure that this SoC supports Zba or Zbb. I asked on the corresponding patchset for Linux and the answer I got, not from the vendor, was that it did. To what extent it might (or if it actually does) I have not yet determined. It's not mentioned in any of the documentation that I have got my hands on. I have one of these boards, so am in the process of getting something functional enough on it to actually test that. Thanks! Conor. --7OlOoqXBjtnjUGFe Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY8mMRAAKCRB4tDGHoIJi 0rFqAP4kzCMgY2FV/i6UGXtiYcCEPlx7nrNk/qTzBH6VSgudlAEAmajARK3/uqrU BbZZzeti/NTkkdZSWxR25ATUDVDQNgo= =erAz -----END PGP SIGNATURE----- --7OlOoqXBjtnjUGFe--