* [PATCH v1 1/3] ARM: dts: npcm8xx: add npcm845 function node
2023-01-17 8:59 [PATCH v1 0/3] add npcm845 function config and dts node Jim Liu
@ 2023-01-17 8:59 ` Jim Liu
2023-01-27 19:07 ` Tom Rini
2023-01-17 8:59 ` [PATCH v1 2/3] ARM: config: enable function for nuvoton npcm845 bmc Jim Liu
2023-01-17 8:59 ` [PATCH v1 3/3] arm: npcm8xx: add security feature header Jim Liu
2 siblings, 1 reply; 7+ messages in thread
From: Jim Liu @ 2023-01-17 8:59 UTC (permalink / raw)
To: JJLIU0, KWLIU, jim.t90615, trini; +Cc: u-boot
Add functaion node list as below:
1. i2c
2. gmac
3. otp
4. aes
5. sha
6. rng
7. serial
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
---
arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 358 +++++++++++++++++++++++
arch/arm/dts/nuvoton-npcm845-evb.dts | 198 +++++++++++++
arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi | 134 +++++++++
3 files changed, 690 insertions(+)
diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
index 4538345dda..fabe5925b7 100644
--- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
@@ -257,6 +257,364 @@
syscon = <&gcr>;
status = "disabled";
};
+
+ i2c1: i2c@81000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x81000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb1_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@82000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x82000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb2_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@83000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x83000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb3_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@84000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x84000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb4_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@85000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x85000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb5_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@86000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x86000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb6_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@87000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x87000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb7_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@88000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x88000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb8_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@89000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x89000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb9_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@8a000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8a000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb10_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@8b000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8b000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb11_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c12: i2c@8c000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8c000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb12_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c13: i2c@8d000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8d000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb13_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c14: i2c@8e000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8e000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb14_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c15: i2c@8f000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0x8f000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb15_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c16: i2c@fff00000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb16_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c17: i2c@fff01000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff01000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb17_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c18: i2c@fff02000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff02000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb18_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c19: i2c@fff03000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff03000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb19_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c20: i2c@fff04000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff04000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb20_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c21: i2c@fff05000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff05000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb21_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c22: i2c@fff06000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff06000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb22_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c23: i2c@fff07000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff07000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb23_pins>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c24: i2c@fff08000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff08000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c25: i2c@fff09000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff09000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
+
+ i2c26: i2c@fff0a000 {
+ compatible = "nuvoton,npcm845-i2c";
+ reg = <0xfff0a000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk NPCM8XX_CLK_APB2>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ syscon = <&gcr>;
+ status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts
index 53f4c6aeca..3cab7807e3 100644
--- a/arch/arm/dts/nuvoton-npcm845-evb.dts
+++ b/arch/arm/dts/nuvoton-npcm845-evb.dts
@@ -11,7 +11,37 @@
aliases {
serial0 = &serial0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ ethernet3 = &gmac3;
i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
+ i2c16 = &i2c16;
+ i2c17 = &i2c17;
+ i2c18 = &i2c18;
+ i2c19 = &i2c19;
+ i2c20 = &i2c20;
+ i2c21 = &i2c21;
+ i2c22 = &i2c22;
+ i2c23 = &i2c23;
+ i2c24 = &i2c24;
+ i2c25 = &i2c25;
+ i2c26 = &i2c26;
spi0 = &fiu0;
spi1 = &fiu1;
spi3 = &fiu3;
@@ -106,6 +136,49 @@
status = "okay";
};
+&gmac0 {
+ phy-mode = "sgmii";
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio5 30 GPIO_ACTIVE_LOW>; /* gpio190 */
+ status = "okay";
+};
+
+&gmac1 {
+ phy-mode = "rgmii-id";
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; /* gpio162 */
+ status = "okay";
+};
+
+&gmac2 {
+ phy-mode = "NC-SI";
+ max-speed = <100>;
+ use-ncsi;
+ pinctrl-0 = <&r1_pins
+ &r1en_pins
+ &r1oen_pins>;
+ status = "disabled";
+};
+
+&gmac3 {
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r2_pins
+ &r2oen_pins
+ &r2en_pins
+ &gpio91o_pins
+ &gpio92o_pins>;
+ snps,bitbang-mii;
+ snps,mdc-gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio91 */
+ snps,mdio-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* gpio92 */
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio93 */
+ status = "okay";
+};
+
&spi1 {
status = "okay";
};
@@ -142,10 +215,135 @@
phys = <&usbphy3 4>;
};
+&rng {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&sha {
+ status = "okay";
+};
+
+&otp {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+ tmp100@48 {
+ compatible = "tmp100";
+ reg = <0x48>;
+ status = "okay";
+ };
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&i2c16 {
+ status = "okay";
+};
+
+&i2c17 {
+ status = "okay";
+};
+
+&i2c18 {
+ status = "okay";
+};
+
+&i2c19 {
+ status = "okay";
+};
+
+&i2c20 {
+ status = "okay";
+};
+
+&i2c21 {
+ status = "okay";
+};
+
+&i2c22 {
+ status = "okay";
+};
+
+&i2c23 {
+ status = "okay";
+};
+
+&i2c24 {
+ status = "okay";
+};
+
+&i2c25 {
+ status = "okay";
+};
+
+&i2c26 {
+ status = "okay";
+};
+
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <
diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
index d21e5042a6..be2ad0cf6c 100644
--- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
+++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
@@ -59,6 +59,68 @@
clocks = <&clk_refclk>;
};
+ gmac0: eth@f0802000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xf0802000 0x0 0x2000>,
+ <0x0 0xf0780000 0x0 0x200>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rg1mdio_pins>;
+ resets = <&rstc2 NPCM8XX_RESET_GMAC1>;
+ status = "disabled";
+ };
+
+ gmac1: eth@f0804000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xf0804000 0x0 0x2000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rg2_pins
+ &rg2mdio_pins>;
+ resets = <&rstc2 NPCM8XX_RESET_GMAC2>;
+ status = "disabled";
+ };
+
+ gmac2: eth@f0806000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xf0806000 0x0 0x2000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r1_pins
+ &r1err_pins
+ &r1md_pins>;
+ resets = <&rstc1 NPCM8XX_RESET_GMAC3>;
+ status = "disabled";
+ };
+
+ gmac3: eth@f0808000 {
+ device_type = "network";
+ compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
+ reg = <0x0 0xf0808000 0x0 0x2000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "stmmaceth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&r2_pins
+ &r2err_pins
+ &r2md_pins>;
+ resets = <&rstc1 NPCM8XX_RESET_GMAC4>;
+ status = "disabled";
+ };
+
ehci1: usb@f0828100 {
compatible = "nuvoton,npcm845-ehci";
reg = <0x0 0xf0828100 0x0 0x1000>;
@@ -236,6 +298,49 @@
status = "disabled";
};
+ serial1: serial@1000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x1000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ status = "disabled";
+ };
+
+ serial2: serial@2000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x2000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ status = "disabled";
+ };
+
+ serial3: serial@3000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x3000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ status = "disabled";
+ };
+
+ serial4: serial@4000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x4000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ status = "disabled";
+ };
+
+ serial5: serial@5000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x5000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ status = "disabled";
+ };
+
+ serial6: serial@6000 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x6000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
gpio0: gpio0@10000 {
compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
reg = <0x10000 0xB0>;
@@ -299,6 +404,35 @@
gpio-controller;
gpio-bank-name = "gpio7";
};
+
+ rng: rng@b000 {
+ compatible = "nuvoton,npcm845-rng";
+ reg = <0xb000 0x8>;
+ status = "disabled";
+ };
+
+ otp: otp@189000 {
+ compatible = "nuvoton,npcm845-otp";
+ reg = <0x189000 0x1000>;
+ status = "disabled";
+ };
+
+ aes: aes@f0858000 {
+ compatible = "nuvoton,npcm845-aes";
+ reg = <0x0 0xf0858000 0x0 0x1000>,
+ <0x0 0xf0851000 0x0 0x1000>;
+ status = "disabled";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "clk_ahb";
+ };
+
+ sha:sha@f085a000 {
+ compatible = "nuvoton,npcm845-sha";
+ reg = <0x0 0xf085a000 0x0 0x1000>;
+ status = "disabled";
+ clocks = <&clk NPCM8XX_CLK_AHB>;
+ clock-names = "clk_ahb";
+ };
};
};
pinctrl: pinctrl@f0800000 {
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v1 3/3] arm: npcm8xx: add security feature header
2023-01-17 8:59 [PATCH v1 0/3] add npcm845 function config and dts node Jim Liu
2023-01-17 8:59 ` [PATCH v1 1/3] ARM: dts: npcm8xx: add npcm845 function node Jim Liu
2023-01-17 8:59 ` [PATCH v1 2/3] ARM: config: enable function for nuvoton npcm845 bmc Jim Liu
@ 2023-01-17 8:59 ` Jim Liu
2023-01-27 19:07 ` Tom Rini
2 siblings, 1 reply; 7+ messages in thread
From: Jim Liu @ 2023-01-17 8:59 UTC (permalink / raw)
To: JJLIU0, KWLIU, jim.t90615, trini; +Cc: u-boot
The NPCM driver can use on npcm7xx/npcm8xx
so add npcm8xx header for driver.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
---
arch/arm/include/asm/arch-npcm8xx/aes.h | 53 ++++++++++++++
arch/arm/include/asm/arch-npcm8xx/otp.h | 93 +++++++++++++++++++++++++
arch/arm/include/asm/arch-npcm8xx/rng.h | 43 ++++++++++++
arch/arm/include/asm/arch-npcm8xx/sha.h | 34 +++++++++
4 files changed, 223 insertions(+)
create mode 100644 arch/arm/include/asm/arch-npcm8xx/aes.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/otp.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/rng.h
create mode 100644 arch/arm/include/asm/arch-npcm8xx/sha.h
diff --git a/arch/arm/include/asm/arch-npcm8xx/aes.h b/arch/arm/include/asm/arch-npcm8xx/aes.h
new file mode 100644
index 0000000000..255efcb5ce
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/aes.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_AES_H_
+#define _NPCM_AES_H_
+
+#define AES_OP_ENCRYPT 0
+#define AES_OP_DECRYPT 1
+#define SIZE_AES_BLOCK (AES128_KEY_LENGTH)
+
+struct npcm_aes_regs {
+ unsigned char reserved_0[0x400]; // 0x000
+ unsigned int aes_key_0; // 0x400
+ unsigned int aes_key_1; // 0x404
+ unsigned int aes_key_2; // 0x408
+ unsigned int aes_key_3; // 0x40c
+ unsigned char reserved_1[0x30]; // 0x410
+ unsigned int aes_iv_0; // 0x440
+ unsigned char reserved_2[0x1c]; // 0x444
+ unsigned int aes_ctr_0; // 0x460
+ unsigned char reserved_3[0x0c]; // 0x464
+ unsigned int aes_busy; // 0x470
+ unsigned char reserved_4[0x04]; // 0x474
+ unsigned int aes_sk; // 0x478
+ unsigned char reserved_5[0x14]; // 0x47c
+ unsigned int aes_prev_iv_0; // 0x490
+ unsigned char reserved_6[0x0c]; // 0x494
+ unsigned int aes_din_dout; // 0x4a0
+ unsigned char reserved_7[0x1c]; // 0x4a4
+ unsigned int aes_control; // 0x4c0
+ unsigned int aes_version; // 0x4c4
+ unsigned int aes_hw_flags; // 0x4c8
+ unsigned char reserved_8[0x28]; // 0x4cc
+ unsigned int aes_sw_reset; // 0x4f4
+ unsigned char reserved_9[0x08]; // 0x4f8
+ unsigned int aes_fifo_data; // 0x500
+ unsigned char reserved_10[0xfc]; // 0x504
+ unsigned int aes_fifo_status; // 0x600
+};
+
+#define AES_BUSY_BIT BIT(0)
+#define SW_RESET_BIT BIT(0)
+#define AES_SK_BIT BIT(0)
+
+#define DIN_FIFO_FULL BIT(0)
+#define DIN_FIFO_EMPTY BIT(1)
+#define DOUT_FIFO_FULL BIT(2)
+#define DOUT_FIFO_EMPTY BIT(3)
+#define DIN_FIFO_OVERFLOW BIT(4)
+#define DOUT_FIFO_UNDERFLOW BIT(5)
+
+int npcm_aes_select_key(u8 fkeyind);
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/otp.h b/arch/arm/include/asm/arch-npcm8xx/otp.h
new file mode 100644
index 0000000000..c8d50fb0ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/otp.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_OTP_H_
+#define _NPCM_OTP_H_
+
+#ifdef CONFIG_ARCH_NPCM8XX
+enum {
+ NPCM_KEY_SA = 0,
+ NPCM_FUSE_SA = 0,
+ NPCM_NUM_OF_SA = 1
+};
+#else
+enum {
+ NPCM_KEY_SA = 0,
+ NPCM_FUSE_SA = 1,
+ NPCM_NUM_OF_SA = 2
+};
+#endif
+
+/* arrray images in flash, to program during fisrt boot (offsets in sector) */
+#define SA_KEYS_FLASH_IMAGE_OFFSET (0x000)
+#define SA_FUSE_FLASH_IMAGE_OFFSET (0x400)
+#define SA_TAG_FLASH_IMAGE_OFFSET (0x800)
+/* F U S E I M G S */
+#define SA_TAG_FLASH_IMAGE_VAL {0x46, 0x55, 0x53, 0x45, 0x49, 0x4d, 0x47, 0x53}
+#define SA_TAG_FLASH_IMAGE_SIZE (8)
+
+#define SA_FUSE_FUSTRAP_OFFSET (0x00)
+#define SA_FUSE_FUSTRAP_OSECBOOT_MASK (0x00800000)
+
+struct npcm_otp_regs {
+ unsigned int fst;
+ unsigned int faddr;
+ unsigned int fdata;
+ unsigned int fcfg;
+ unsigned int fustrap_fkeyind;
+ unsigned int fctl;
+};
+
+#define FST_RDY BIT(0)
+#define FST_RDST BIT(1)
+#define FST_RIEN BIT(2)
+
+#ifdef CONFIG_ARCH_NPCM8XX
+#define FADDR_BYTEADDR(addr) ((addr) << 3)
+#define FADDR_BITPOS(pos) ((pos) << 0)
+#define FADDR_VAL(addr, pos) (FADDR_BITPOS(pos) | FADDR_BYTEADDR(addr))
+#define FADDR_IN_PROG BIT(16)
+#else
+#define FADDR_BYTEADDR(addr) ((addr) << 0)
+#define FADDR_BITPOS(pos) ((pos) << 10)
+#define FADDR_VAL(addr, pos) (FADDR_BYTEADDR(addr) | FADDR_BITPOS(pos))
+#endif
+
+#define FDATA_MASK (0xff)
+
+#define FUSTRAP_O_SECBOOT BIT(23)
+#define FCFG_FDIS BIT(31)
+#define FKEYIND_KVAL BIT(0)
+#define FKEYIND_KSIZE_MASK (0x00000070)
+#define FKEYIND_KSIZE_128 (0x4 << 4)
+#define FKEYIND_KSIZE_192 (0x5 << 4)
+#define FKEYIND_KSIZE_256 (0x6 << 4)
+#define FKEYIND_KIND_MASK (0x000c0000)
+#define FKEYIND_KIND_KEY(indx) ((indx) << 18)
+
+/* Program cycle initiation values (sequence of two adjacent writes) */
+#define PROGRAM_ARM 0x1
+#define PROGRAM_INIT 0xBF79E5D0
+
+/* Read cycle initiation value */
+#define READ_INIT 0x02
+
+/* Value to clean FDATA contents */
+#define FDATA_CLEAN_VALUE 0x01
+
+#ifdef CONFIG_ARCH_NPCM8XX
+#define NPCM_OTP_ARR_BYTE_SIZE 8192
+#else
+#define NPCM_OTP_ARR_BYTE_SIZE 1024
+#endif
+
+#define MIN_PROGRAM_PULSES 4
+#define MAX_PROGRAM_PULSES 20
+
+int fuse_prog_image(u32 bank, uintptr_t address);
+int fuse_program_data(u32 bank, u32 word, u8 *data, u32 size);
+int npcm_otp_select_key(u8 key_index);
+bool npcm_otp_is_fuse_array_disabled(u32 arr);
+void npcm_otp_nibble_parity_ecc_encode(u8 *datain, u8 *dataout, u32 size);
+void npcm_otp_majority_rule_ecc_encode(u8 *datain, u8 *dataout, u32 size);
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/rng.h b/arch/arm/include/asm/arch-npcm8xx/rng.h
new file mode 100644
index 0000000000..897e8fea82
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/rng.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_RNG_H_
+#define _NPCM_RNG_H_
+
+struct npcm_rng_regs {
+ unsigned int rngcs;
+ unsigned int rngd;
+ unsigned int rngmode;
+};
+
+#define RNGCS_RNGE (1 << 0)
+#define RNGCS_DVALID (1 << 1)
+#define RNGCS_CLKP(range) ((0x0f & (range)) << 2)
+#define RNGMODE_M1ROSEL_VAL (0x02) /* Ring Oscillator Select for Method I */
+
+/*----------------------------------------------------------------------------*/
+/* Core Domain Clock Frequency Range for the selected value is higher */
+/* than or equal to the actual Core domain clock frequency */
+/*----------------------------------------------------------------------------*/
+enum {
+ RNG_CLKP_80_100_MHZ = 0x00, /*default */
+ RNG_CLKP_60_80_MHZ = 0x01,
+ RNG_CLKP_50_60_MHZ = 0x02,
+ RNG_CLKP_40_50_MHZ = 0x03,
+ RNG_CLKP_30_40_MHZ = 0x04,
+ RNG_CLKP_25_30_MHZ = 0x05,
+ RNG_CLKP_20_25_MHZ = 0x06,
+ RNG_CLKP_5_20_MHZ = 0x07,
+ RNG_CLKP_2_15_MHZ = 0x08,
+ RNG_CLKP_9_12_MHZ = 0x09,
+ RNG_CLKP_7_9_MHZ = 0x0A,
+ RNG_CLKP_6_7_MHZ = 0x0B,
+ RNG_CLKP_5_6_MHZ = 0x0C,
+ RNG_CLKP_4_5_MHZ = 0x0D,
+ RNG_CLKP_3_4_MHZ = 0x0E,
+ RNG_NUM_OF_CLKP
+};
+
+void npcm_rng_init(void);
+void npcm_rng_disable(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/sha.h b/arch/arm/include/asm/arch-npcm8xx/sha.h
new file mode 100644
index 0000000000..ec0ec9ce1f
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/sha.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_SHA_H_
+#define _NPCM_SHA_H_
+
+#define HASH_DIG_H_NUM 8
+
+/* SHA type */
+enum npcm_sha_type {
+ npcm_sha_type_sha2 = 0,
+ npcm_sha_type_sha1,
+ npcm_sha_type_num
+};
+
+struct npcm_sha_regs {
+ unsigned int hash_data_in;
+ unsigned char hash_ctr_sts;
+ unsigned char reserved_0[0x03];
+ unsigned char hash_cfg;
+ unsigned char reserved_1[0x03];
+ unsigned char hash_ver;
+ unsigned char reserved_2[0x13];
+ unsigned int hash_dig[HASH_DIG_H_NUM];
+};
+
+#define HASH_CTR_STS_SHA_EN BIT(0)
+#define HASH_CTR_STS_SHA_BUSY BIT(1)
+#define HASH_CTR_STS_SHA_RST BIT(2)
+#define HASH_CFG_SHA1_SHA2 BIT(0)
+
+int npcm_sha_calc(u8 type, const u8 *buf, u32 len, u8 *digest);
+int npcm_sha_selftest(u8 type);
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread