From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7789C38142 for ; Tue, 31 Jan 2023 07:07:24 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B66D8857C8; Tue, 31 Jan 2023 08:07:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7D001857CC; Tue, 31 Jan 2023 08:07:20 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1821785798 for ; Tue, 31 Jan 2023 08:07:16 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 30V779UG086757 for ; Tue, 31 Jan 2023 15:07:09 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Tue, 31 Jan 2023 15:07:05 +0800 Date: Tue, 31 Jan 2023 07:07:02 +0000 From: Leo Liang To: Yu Chien Peter Lin CC: , Subject: Re: [PATCH 05/11] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() Message-ID: References: <20230119070544.7423-1-peterlin@andestech.com> <20230119070544.7423-6-peterlin@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20230119070544.7423-6-peterlin@andestech.com> User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 30V779UG086757 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Peter, On Thu, Jan 19, 2023 at 03:05:38PM +0800, Yu Chien Peter Lin wrote: > This patch improves the cache enabling operation in harts_early_init(), > also moves the CSR definition to include/asm/arch-andes/csr.h and drops > unnecessary i/d-cache disable functions from cleanup_before_linux(). > > Signed-off-by: Yu Chien Peter Lin > --- > arch/riscv/cpu/ax25/cpu.c | 46 +++++++------------------ > arch/riscv/include/asm/arch-andes/csr.h | 29 ++++++++++++++++ > 2 files changed, 42 insertions(+), 33 deletions(-) > create mode 100644 arch/riscv/include/asm/arch-andes/csr.h > > diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c > index c4c2de2ef0..d335b8d0a8 100644 > --- a/arch/riscv/cpu/ax25/cpu.c > +++ b/arch/riscv/cpu/ax25/cpu.c > @@ -1,6 +1,6 @@ > void harts_early_init(void) > { > + /* Enable I/D-cache in SPL */ > if (CONFIG_IS_ENABLED(RISCV_MMODE)) { > - unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); > + unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); > + > + mcache_ctl_val |= MCACHE_CTL_DC_COHEN; > + mcache_ctl_val |= MCACHE_CTL_IC_EN; > + mcache_ctl_val |= MCACHE_CTL_DC_EN; These three could be combined into one statement. With your consent, I could modify this when applying to u-boot-riscv/master. Reviewed-by: Leo Yu-Chi Liang > > - if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) > - mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN; > - if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN)) > - mcache_ctl_val |= V5_MCACHE_CTL_IC_EN; > - if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN)) > - mcache_ctl_val |= V5_MCACHE_CTL_DC_EN; > csr_write(CSR_MCACHE_CTL, mcache_ctl_val); > > /* > - * Check DC_COHEN_EN, if cannot write to mcache_ctl, > - * we assume this bitmap not support L2 CM > + * Check mcache_ctl.DC_COHEN, we assume this platform does > + * not support CM if the bit is hard-wired to 0. > */ > - mcache_ctl_val = csr_read(CSR_MCACHE_CTL); > - if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) { > - /* Wait for DC_COHSTA bit be set */ > - while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN)) > - mcache_ctl_val = csr_read(CSR_MCACHE_CTL); > + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { > + /* Wait for DC_COHSTA bit to be set */ > + while (!(csr_read(CSR_MCACHE_CTL)& MCACHE_CTL_DC_COHSTA)); > } > } > } Best regards, Leo