[PATCH 07/11] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL

Yu Chien Peter Lin
2023-01-19T07:07:38Z

This patch refines L1 cache enable/disable and v5l2-cache enable
functions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
arch/riscv/cpu/ax25/cache.c | 100 ++++++++++++++++++++++++------------
1 file changed, 68 insertions(+), 32 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 1c0c3772a1..ed12c83e7e 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -1,57 +1,49 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Andes Technology Corporation
+ * Copyright (C) 2023 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/

+#include <asm/csr.h>
+#include <asm/asm.h>
#include <common.h>
+#include <cache.h>
#include <cpu_func.h>
#include <dm.h>
-#include <asm/cache.h>
#include <dm/uclass-internal.h>
-#include <cache.h>
-#include <asm/csr.h>
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-/* mcctlcommand */
-#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
+#include <asm/arch-andes/csr.h>

-/* D-cache operation */
-#define CCTL_L1D_WBINVAL_ALL 6
-#endif
-#endif
-
-#ifdef CONFIG_V5L2_CACHE
-static void _cache_enable(void)
+void enable_caches(void)
{
- struct udevice *dev = NULL;
-
- uclass_find_first_device(UCLASS_CACHE, &dev);
-
- if (dev)
- cache_enable(dev);
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CACHE,
+ DM_DRIVER_GET(v5l2_cache),
+ &dev);
+ if (ret) {
+ log_debug("Cannot enable v5l2 cache\n");
+ } else {
+ ret = cache_enable(dev);
+ if (ret)
+ log_debug("v5l2 cache enable failed\n");
+ }
}

-static void _cache_disable(void)
+static void cache_ops(int (*ops)(struct udevice *dev))
{
struct udevice *dev = NULL;

uclass_find_first_device(UCLASS_CACHE, &dev);

if (dev)
- cache_disable(dev);
+ ops(dev);
}
-#endif

void flush_dcache_all(void)
{
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
#if CONFIG_IS_ENABLED(RISCV_MMODE)
- csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
-#endif
-#endif
+ csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
#endif
}

@@ -67,26 +59,70 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)

void icache_enable(void)
{
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL));
+#endif
}

void icache_disable(void)
{
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL));
+#endif
}

void dcache_enable(void)
{
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
+#endif
+
+#ifdef CONFIG_V5L2_CACHE
+ cache_ops(cache_enable);
+#endif
}

void dcache_disable(void)
{
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
+#endif
+
+#ifdef CONFIG_V5L2_CACHE
+ cache_ops(cache_disable);
+#endif
}

int icache_status(void)
{
- return 0;
+ int ret = 0;
+
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ asm volatile (
+ "csrr t1, %1\n\t"
+ "andi %0, t1, 0x01\n\t"
+ : "=r" (ret)
+ : "i"(CSR_MCACHE_CTL)
+ : "memory"
+ );
+#endif
+
+ return !!ret;
}

int dcache_status(void)
{
- return 0;
+ int ret = 0;
+
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
+ asm volatile (
+ "csrr t1, %1\n\t"
+ "andi %0, t1, 0x02\n\t"
+ : "=r" (ret)
+ : "i" (CSR_MCACHE_CTL)
+ : "memory"
+ );
+#endif
+
+ return !!ret;
}
--
2.34.1