[PATCH 04/11] driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform

Yu Chien Peter Lin
2023-01-19T07:07:00Z

The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
drivers/cache/cache-v5l2.c | 32 ++++++++++++++++++++++++--------
1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
index bbdb76bd57..e782430c57 100644
--- a/drivers/cache/cache-v5l2.c
+++ b/drivers/cache/cache-v5l2.c
@@ -34,6 +34,14 @@ struct l2cache {
volatile u64 cctl_status;
};

+/* Configuration register */
+#define MEM_MAP_OFF 20
+#define MEM_MAP_MSK BIT(MEM_MAP_OFF)
+/* offset of v0 memory map (Gen1) */
+static u32 cmd_stride = 0x10;
+static u32 status_stride = 0x0;
+static u32 status_bit_offset = 0x4;
+
/* Control Register */
#define L2_ENABLE 0x1
/* prefetch */
@@ -53,14 +61,15 @@ struct l2cache {
#define DRAMICTL_MSK BIT(DRAMICTL_OFF)

/* CCTL Command Register */
-#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
+#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * (cmd_stride))
#define L2_WBINVAL_ALL 0x12

/* CCTL Status Register */
-#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
-#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
-#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
-#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
+#define CCTL_STATUS_REG(base, hart) ((ulong)(base) + 0x80 + (hart) * (status_stride))
+#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * (status_bit_offset)))
+#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * (status_bit_offset)))
+#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * (status_bit_offset)))
+#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * (status_bit_offset)))

DECLARE_GLOBAL_DATA_PTR;

@@ -133,12 +142,19 @@ static int v5l2_probe(struct udevice *dev)
{
struct v5l2_plat *plat = dev_get_plat(dev);
struct l2cache *regs = plat->regs;
- u32 ctl_val;
+ u32 cfg_val, ctl_val;

+ cfg_val = readl(&regs->configure);
ctl_val = readl(&regs->control);

- if (!(ctl_val & L2_ENABLE))
- ctl_val |= L2_ENABLE;
+ /* If true, v1 memory map (Gen2) */
+ if (cfg_val & MEM_MAP_MSK) {
+ cmd_stride = 0x1000;
+ status_stride = 0x1000;
+ status_bit_offset = 0x0;
+ }
+
+ ctl_val |= L2_ENABLE;

if (plat->iprefetch != -EINVAL) {
ctl_val &= ~(IPREPETCH_MSK);
--
2.34.1