* [PATCH v2] riscv: ae350: Enable CCTL_SUEN
@ 2023-01-03 8:17 Rick Chen
2023-01-31 14:57 ` Leo Liang
0 siblings, 1 reply; 2+ messages in thread
From: Rick Chen @ 2023-01-03 8:17 UTC (permalink / raw)
To: bmeng.cn, ycliang, rick, rickchen36; +Cc: u-boot
CCTL operations are available to Supervisor/User-mode
software under the control of the mcache_ctl.CCTL_SUEN
control bit. Enable it to support Supervisor(and User)
CCTL operations.
Signed-off-by: Rick Chen <rick@andestech.com>
---
Changes in v2
- fix typo
- correct aligment
---
arch/riscv/cpu/ax25/cpu.c | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index c4c2de2ef0..a46674f7c2 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -12,18 +12,20 @@
#include <asm/csr.h>
#define CSR_MCACHE_CTL 0x7ca
-#define CSR_MMISC_CTL 0x7d0
-#define CSR_MARCHID 0xf12
+#define CSR_MMISC_CTL 0x7d0
+#define CSR_MARCHID 0xf12
#define V5_MCACHE_CTL_IC_EN_OFFSET 0
#define V5_MCACHE_CTL_DC_EN_OFFSET 1
-#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
+#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
+#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
-#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
+#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
+#define V5_MCACHE_CTL_CCTL_SUEN BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
/*
@@ -55,6 +57,8 @@ void harts_early_init(void)
mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
+ mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
/*
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] riscv: ae350: Enable CCTL_SUEN
2023-01-03 8:17 [PATCH v2] riscv: ae350: Enable CCTL_SUEN Rick Chen
@ 2023-01-31 14:57 ` Leo Liang
0 siblings, 0 replies; 2+ messages in thread
From: Leo Liang @ 2023-01-31 14:57 UTC (permalink / raw)
To: Rick Chen; +Cc: u-boot
On Tue, Jan 03, 2023 at 04:17:13PM +0800, Rick Chen wrote:
> CCTL operations are available to Supervisor/User-mode
> software under the control of the mcache_ctl.CCTL_SUEN
> control bit. Enable it to support Supervisor(and User)
> CCTL operations.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> ---
>
> Changes in v2
> - fix typo
> - correct aligment
>
> ---
>
> arch/riscv/cpu/ax25/cpu.c | 18 +++++++++++-------
> 1 file changed, 11 insertions(+), 7 deletions(-)
>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2023-01-31 14:58 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-01-03 8:17 [PATCH v2] riscv: ae350: Enable CCTL_SUEN Rick Chen
2023-01-31 14:57 ` Leo Liang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox