From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D92CC38142 for ; Wed, 1 Feb 2023 06:52:52 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 00B5F85BF8; Wed, 1 Feb 2023 07:52:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 17C3A85C05; Wed, 1 Feb 2023 07:52:49 +0100 (CET) Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A4A4985BEB for ; Wed, 1 Feb 2023 07:52:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ycliang@andestech.com Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3116qbjs038618; Wed, 1 Feb 2023 14:52:37 +0800 (+08) (envelope-from ycliang@andestech.com) Received: from ubuntu01 (10.0.12.75) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 1 Feb 2023 14:52:35 +0800 Date: Wed, 1 Feb 2023 06:52:29 +0000 From: Leo Liang To: Nikita Shubin CC: Nikita Shubin , Rick Chen , "Simon Glass" , Subject: Re: [RFC PATCH] riscv: cpu: check U-Mode before counteren write Message-ID: References: <20221214055843.7177-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20221214055843.7177-1-nikita.shubin@maquefel.me> User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.75] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3116qbjs038618 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On Wed, Dec 14, 2022 at 08:58:43AM +0300, Nikita Shubin wrote: > From: Nikita Shubin > > The Priv ISA states: > "In systems without U-mode, the mcounteren register should > not exist." > > Check U-Mode is present in MISA before writing to counteren, otherwise > we endup with Illegal Instruction exception on systems without U-Mode. > > Also make checking MISA default for M-Mode. > > Signed-off-by: Nikita Shubin > --- > This seems obvious at first glance, but i've never seen 'u' extension > enywhere in "riscv,isa" device tree property, even qemu doesn't set this, > and if we simply enable this check - this will break existing board for sure. > > We can rely on MISA completely if we are in M-Mode, as we currently check only > 'd', 'f' and 'u', which are standart and nothing fancy. > --- > arch/riscv/cpu/cpu.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) Reviewed-by: Leo Yu-Chi Liang