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Tue, 7 Sep 2021 16:21:02 +0800 (GMT-8) (envelope-from ycliang@andestech.com) Received: from ubuntu02 (10.0.12.212) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Tue, 7 Sep 2021 16:21:00 +0800 Date: Tue, 7 Sep 2021 16:20:50 +0800 From: Leo Liang To: CC: , Subject: [PULL] u-boot-riscv/master Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline User-Agent: Mutt/2.0.5 (2021-01-21) X-Originating-IP: [10.0.12.212] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 1878L2eZ070945 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Tom, The following changes since commit ad320c237bea7ece659efaf6c1d43475e0e5db6a: Merge tag 'u-boot-stm32-20210906' of https://source.denx.de/u-boot/custodians/u-boot-stm (2021-09-06 10:31:56 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 30fa33dc808b8f28185bca9c812225cbc1ec6e8f: riscv: lib: modify the indent (2021-09-07 10:34:29 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/9018 ---------------------------------------------------------------- Heinrich Schuchardt (3): riscv: enable booting HiFive Unmatched from SATA configs: qemu-riscvXX_spl_defconfig enable CMD_SBI riscv: show code leading to exception Thomas Skibo (1): riscv: Add missing sentinel in ocores_i2c.c Zong Li (5): cache: add sifive composable cache driver common: board_r: support enable_caches for RISC-V riscv: lib: implement enable_caches for sifive cache board: sifive: use ccache driver instead of helper function riscv: lib: modify the indent arch/riscv/Kconfig | 5 +++ arch/riscv/cpu/fu540/Kconfig | 2 + arch/riscv/cpu/fu540/Makefile | 1 - arch/riscv/cpu/fu540/cache.c | 55 ----------------------- arch/riscv/cpu/fu740/Kconfig | 2 + arch/riscv/cpu/fu740/Makefile | 1 - arch/riscv/cpu/fu740/cache.c | 55 ----------------------- arch/riscv/include/asm/arch-fu540/cache.h | 14 ------ arch/riscv/include/asm/arch-fu740/cache.h | 14 ------ arch/riscv/include/asm/cache.h | 2 +- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/cache.c | 4 ++ arch/riscv/lib/interrupts.c | 33 ++++++++++++++ arch/riscv/lib/sifive_cache.c | 27 +++++++++++ board/sifive/unleashed/unleashed.c | 10 +---- board/sifive/unmatched/unmatched.c | 11 ++--- common/board_r.c | 4 +- configs/qemu-riscv32_spl_defconfig | 1 + configs/qemu-riscv64_spl_defconfig | 1 + configs/sifive_unmatched_defconfig | 5 +++ drivers/cache/Kconfig | 7 +++ drivers/cache/Makefile | 1 + drivers/cache/cache-sifive-ccache.c | 75 +++++++++++++++++++++++++++++++ drivers/i2c/ocores_i2c.c | 1 + include/configs/sifive-unmatched.h | 3 ++ 25 files changed, 176 insertions(+), 159 deletions(-) delete mode 100644 arch/riscv/cpu/fu540/cache.c delete mode 100644 arch/riscv/cpu/fu740/cache.c delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h create mode 100644 arch/riscv/lib/sifive_cache.c create mode 100644 drivers/cache/cache-sifive-ccache.c Best regards, Leo