From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D267CC433EF for ; Fri, 28 Jan 2022 18:19:27 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 96BA6820F8; Fri, 28 Jan 2022 19:19:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aurel32.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; secure) header.d=aurel32.net header.i=@aurel32.net header.b="f/NvP8m8"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 41F32820FE; Fri, 28 Jan 2022 19:19:24 +0100 (CET) Received: from hall.aurel32.net (hall.aurel32.net [IPv6:2001:bc8:30d7:100::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7E4A382014 for ; Fri, 28 Jan 2022 19:19:21 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aurel32.net Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=aurelien@aurel32.net DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=In-Reply-To:Content-Transfer-Encoding:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=RJdOEWryJRpDv0tfbh7HctbUaDxrPIjC9ncjMeZZJGk=; b=f/NvP8m8eJbJIKNyT98e/wr0YZ tAsoiCOteLOu21knt8U7tl4KFXb2eAvPbUTIERUxomKrWivf5VS5yfb4wbfdLPlyi8c7cpFadXyPE CIh74sjQqGIKYfqSjfOI3y7vHeyo6/tacgccIQve5NT3HLOUKBFc6vDY6lcgEmmyV1OggzJq16Otc 6a8+AUq7WI9mKb37RZaDuVQo6HJwcfM3f43OpxlzZCXkq+D2iXwoqsu80G4XZ8lgN7Nw+/azEoph7 8qvWKKIGNvSMCz10FePYGrisFv6LOoenkm7S4sp8EoTB+9B3Dpes/549J/iZGN02lEGjs5oC0M6zi MdPgm93A==; Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nDVqB-000dw8-Lp; Fri, 28 Jan 2022 19:19:19 +0100 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.95) (envelope-from ) id 1nDVqB-007rkm-7b; Fri, 28 Jan 2022 19:19:19 +0100 Date: Fri, 28 Jan 2022 19:19:19 +0100 From: Aurelien Jarno To: Heinrich Schuchardt Cc: Alexandre Ghiti , Rick Chen , Leo , u-boot@lists.denx.de, matthias.klose@canonical.com Subject: Re: [PATCH] riscv: Fix build against binutils 2.38 Message-ID: References: <20220128134713.2322800-1-alexandre.ghiti@canonical.com> <23463906-3c57-8ea7-d70f-b31978cfa0bb@canonical.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <23463906-3c57-8ea7-d70f-b31978cfa0bb@canonical.com> User-Agent: Mutt/2.1.4 (2021-12-11) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On 2022-01-28 19:03, Heinrich Schuchardt wrote: > On 1/28/22 14:47, Alexandre Ghiti wrote: > > The following description is copied from the equivalent patch for the > > Linux Kernel proposed by Aurelien Jarno: > >=20 > > From version 2.38, binutils default to ISA spec version 20191213. This > > means that the csr read/write (csrr*/csrw*) instructions and fence.i > > instruction has separated from the `I` extension, become two standalone > > extensions: Zicsr and Zifencei. As the kernel uses those instruction, > > this causes the following build failure: > >=20 > > arch/riscv/cpu/mtrap.S: Assembler messages: > > arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' > > arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' > > arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' > > arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' >=20 > I tried to build qemu-riscv64_smode_defconfig. With your patch I get >=20 > arch/riscv/cpu/cpu.c: Assembler messages: > arch/riscv/cpu/cpu.c:94: Error: unrecognized opcode `csrs sstatus,a5' > arch/riscv/cpu/cpu.c:95: Error: unrecognized opcode `csrw 0x003,0' >=20 > The build flag used is -march=3Drv64imac. >=20 > My toolchain is: > binutils 2.37.90.20220126-0ubuntu1 > riscv64-linux-gnu-gcc (Ubuntu 10.3.0-8ubuntu1) 10.3.0 >=20 > This GCC does not support _zicsr_zifencei: > cc1: error: =E2=80=98-march=3Drv64imac_zicsr_zifencei=E2=80=99: unsupport= ed ISA subset =E2=80=98z >=20 > Could it be that the GCC is too old for the new binutils? > When was the z subset added to GCC? Yes, GCC 11 is the minimum version that understand those extensions. --=20 Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net