From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05C0DC433EF for ; Thu, 16 Jun 2022 19:15:47 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 15C6984337; Thu, 16 Jun 2022 21:15:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="mogK/VzT"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0C053842C7; Thu, 16 Jun 2022 21:15:43 +0200 (CEST) Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3A34E842C7 for ; Thu, 16 Jun 2022 21:15:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=lee.jones@linaro.org Received: by mail-pj1-x1030.google.com with SMTP id 73-20020a17090a0fcf00b001eaee69f600so2315376pjz.1 for ; Thu, 16 Jun 2022 12:15:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=SW3CVblRKsNIJztjiYOy1fs8l8WlX3I+r40SSDsuh0g=; b=mogK/VzT1MhncFpHOz6Si8LLb0Ppcr9BQSQ9wTlZjmgBIjjga91GhmNC61BmArDAAO FmbeKYhc0pq/SVrg34edOj02Xc7bOVOvS0FkxttqTVoVcJHGintw/syfcAM45KDBC7Se SATFMQ1v7OfhQ9+scT/OZWo6+fxXzXDClJmJT0eDMfVPScVZe1GzFRazg6ZefeUJbLFm ddePlTXvtxc9JpWbfu3X7if+1uF67nZKwd/XpWyCqwqr6qZ+BsfNfIQ86jpcGjQvnFBP Jeiiq2RwJxqRjdS9PAEUKMommAuzaaEfYEws1Mq6hUbGbpQSBy0jsgiQ7P06wsVscye8 gY8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=SW3CVblRKsNIJztjiYOy1fs8l8WlX3I+r40SSDsuh0g=; b=ChY98e5BgcBUwe5OpaoB/6+gJsPMEvdLZhMIEoNr5X4NyQU/YhjIca0u0DVYpcy5l0 2QuFvXmoGkptICsEIBxtmwWyC+sbYcoDdvy4+6Y+iBo+jgHNGcpxoXGozwPNvsNSFFCQ a0/gSVy8LGfj01iA+OSBma88MGGt+UIj9LEmooGHlv/XkoAmjYZJF9GVsBdu6wGlonNs RQMUbvBWEt0bpj2pYpaJi5gnIQQ/L3CGuy9CHZIXrbRKGdoh3SmulYVpNhKm5azfzJsp 0IdoL7se+5xDuXCFRXuu05vf+zoIgHsgepEfqjRGICmxzZ2zwaH8WljRcCBo6k4P5vrK XfbA== X-Gm-Message-State: AJIora9diu8/+7b7iKCG1+TIfxFDuP5Dq4fezwLlQdrUW591HgPkU9/Y zNPRalEyAs3hmabkrk78nI2Ub9GHAIgVxkH8 X-Google-Smtp-Source: AGRyM1uBzS6iIn9IM5+i+MBXOcVmeHMOz/mLE7jKmrKzp3E0cD3EC1UQIC93/GSnNy6Xc8jTvwuWRA== X-Received: by 2002:a17:90b:4c8f:b0:1e6:9bf9:1ab8 with SMTP id my15-20020a17090b4c8f00b001e69bf91ab8mr6465053pjb.215.1655406936929; Thu, 16 Jun 2022 12:15:36 -0700 (PDT) Received: from google.com ([192.77.111.2]) by smtp.gmail.com with ESMTPSA id je6-20020a170903264600b0015e8d4eb1fasm2013185plb.68.2022.06.16.12.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jun 2022 12:15:36 -0700 (PDT) Date: Thu, 16 Jun 2022 20:15:29 +0100 From: Lee Jones To: u-boot@lists.denx.de, linux-rockchip@lists.infradead.org Cc: wxt@rock-chips.com, kever.yang@rock-chips.com, zhangqing@rock-chips.com, derrick.huang@rock-chips.com, chenjh@rock-chips.com, hisping.lin@rock-chips.com, typ@rock-chips.com, cwz@rock-chips.com, chenfen@rock-chips.com, jagan@amarulasolutions.com, sjg@chromium.org, cym@rock-chips.com, pgwipeout@gmail.com, adelva@google.com, rammuthiah@google.com Subject: Re: [Rock Pi 4+] Mainline LPDDR4 RAM initialisation is not sufficient to boot successfully Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Wed, 25 May 2022, Lee Jones wrote: > Good afternoon, > > There appear to be a number of issues with the Rockchip rk3399 DDR RAM > initialisation sequence in Mainline. Specifically, I'm seeing > consistent failures on the Rock Pi 4+ during early boot. Can anyone from Rockchip help with this please? What does the binary blob [0] do differently to the U-boot implementation. Are you able to publish the source for the DDR binary blob? Please help me fix U-boot. [0] https://github.com/rockchip-linux/rkbin/blob/master/bin/rk33/rk3399_ddr_933MHz_v1.25.bin > A typical failure looks something like this: > > U-Boot TPL 2022.07-rc3-00005-g1b04a961c6 (May 25 2022 - 11:09:19) > Channel 0: LPDDR4, 50MHz > BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB > Channel 1: col error > Cap error! > 256B stride > lpddr4_set_rate: change freq to 400000000 mhz 0, 1 > lpddr4_set_rate: change freq to 800000000 mhz 1, 0 > Trying to boot from BOOTROM > Returning to boot ROM... > > Even when the system boots to a terminal, which happens very > infrequently, the LPDDR4 RAM chip at Channel 1 can have conflicting > discovery information printed during TPL. The following 3 lines were > printed during successive reboots using the same SD card with no > changes: > > # Boot 1: > BW=32 Col=9 Bk=4 CS0 Row=16/15 CS=1 Die BW=16 Size=384MB > > # Boot 2: > BW=32 Col=10 Bk=4 CS0 Row=16/15 CS=1 Die BW=16 Size=768MB > > # Boot 3: > BW=32 Col=10 Bk=4 CS0 Row=15 CS=1 Die BW=16 Size=512MB > > The story changes when I build the idbloader.img image with Rockchip's > TBL (?) binary blob [0]. With that built in, presumably in place of > the upstream TBL, both RAM chips are successfully enumerated and boot > succeeds with 100% success rate: > > tools/mkimage -n rk3399 -T rksd -d \ > rk3399_ddr_933MHz_v1.25.bin:spl/u-boot-spl.bin idbloader.img > > Another thing that is very different between the 2 is the initial > frequency the LPDDR4 chips are clocked at. Using the upstream TBL > version, the default is 50Mhz, which seems very low. If using the > Rockchip supplied binary blob file, this is increased to a respectable > 416MHz: > > # Mainline > Channel 0: LPDDR4, 50MHz > > # Rockchip TBL blob > Channel 0: LPDDR4,416MHz > > One thing I did try was to load in the 400Mhz configuration settings > from drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc as the default > initial values, instead of the 50MHz default taken from > arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi, but this failed in a number > of ways: > > Setting clock: Freq: 400MHz (400000000) > Calling SDRAM init: 2 Channels > Starting SDRAM initialization... > mr5:0 mr12:0 mr14:0 > Training failed for rank 2, ch 0 (ret: -22) > mr5:0 mr12:0 mr14:0 > Training failed for rank 1, ch 0 (ret: -22) > mr5:0 mr12:0 mr14:0 > Training failed for rank 2, ch 1 (ret: -22) > mr5:0 mr12:0 mr14:0 > Training failed for rank 1, ch 1 (ret: -22) > Rank for Channel 1 is 0x0 > Rank for Channel 0 is 0x0 > Rank for Channel 1 is 0x0 > sdram_init: LPDDR4 - 400MHz failed! > rk3399_dmc_init DRAM init failed -22 > > So my question is; does Rockchip, or anyone else for that matter, have > any plans on updating Mainline U-Boot with the upgraded/working LPDDR4 > initialisation sequence? > > As ever, any information / help would be gratefully received. > > NB: If I have missed any critical people out from this discussion, > please feel free to loop as many of them in as you see fit. > > Kind regards, > Lee > > [0] https://github.com/rockchip-linux/rkbin/blob/master/bin/rk33/rk3399_ddr_933MHz_v1.25.bin > -- Lee Jones [李琼斯] Principal Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog