Re: [SPAM] rk3399 TPL memory setup code triggers clock frequency limit assertion

[Xavier Drudis Ferran <xdrudis@tinet.cat>]

El Sun, Aug 07, 2022 at 04:44:04PM +0200, Michal Suchánek deia:
> Hello,
> 
> when compiled with clock debug rk3399 cannot be booted because memory
> setup code triggers clock assertion:
> 
> U-Boot TPL 2022.07-00038-g61e11a8e9f-dirty (Aug 07 2022 - 16:13:17)
> TPL PLL at ff760000: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz
> TPL PLL at ff760020: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz
> TPL PLL at ff760080: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz
> TPL PLL at ff760060: fbdiv=64, refdiv=1, postdiv1=2, postdiv2=2, vco=1536000 khz, output=384000 khz
> TPL PLL at ff760040: fbdiv=12, refdiv=1, postdiv1=3, postdiv2=2, vco=288000 khz, output=48000 khz
> drivers/clk/rockchip/clk_rk3399.c:347: rkclk_set_pll: Assertion `vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX' failed.Channel 0: LPDDR4, 50MHz

Sorry, I don't have time now. But It might be related to 

https://patchwork.ozlabs.org/project/uboot/patch/20220716103144.GA2167@begut/

Apparently this clock is wrong but nobody finds any consequence of it being wrong. 
If one asks for a 50MHz clock and gets a 48MHz clockthings might work anyway, but 
it's nice that at least when one asks to be told of problems one is told.


> 
> What would be a resonable way to make rk3399 bootable with clock debug
> enabled?
>

Try my patch, I don't think it can hurt ?