Re: [PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock

[Jorge Ramirez <jorge.ramirez@oss.qualcomm.com>]

On 07/04/25 14:36:51, neil.armstrong@linaro.org wrote:
> On 07/04/2025 14:05, Jorge Ramirez-Ortiz wrote:
> > Select the right clock for sdhci.
> > 
> > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
> > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> > ---
> >   drivers/clk/qcom/clock-apq8096.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
> > index bc00826a5e8..551f52d5197 100644
> > --- a/drivers/clk/qcom/clock-apq8096.c
> > +++ b/drivers/clk/qcom/clock-apq8096.c
> > @@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
> >   	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> >   	switch (clk->id) {
> > -	case GCC_SDCC1_APPS_CLK: /* SDC1 */
> > +	case GCC_SDCC2_APPS_CLK: /* SDC2 */
> 
> Should be GCC_SDCC2_AHB_CLK

why? also if I do that, mcc fails to probe

> 
> >   		return clk_init_sdc(priv, rate);
> >   		break;
> >   	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
>