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[79.144.185.233]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1795db7sm140038905e9.25.2025.04.07.08.27.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 08:27:13 -0700 (PDT) From: Jorge Ramirez X-Google-Original-From: Jorge Ramirez Date: Mon, 7 Apr 2025 17:27:12 +0200 To: neil.armstrong@linaro.org Cc: Jorge Ramirez , caleb.connolly@linaro.org, sumit.garg@kernel.org, u-boot-qcom@groups.io, u-boot@lists.denx.de Subject: Re: [PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock Message-ID: References: <20250407120536.236003-1-jorge.ramirez@oss.qualcomm.com> <20250407120536.236003-3-jorge.ramirez@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-ORIG-GUID: MMSXNWqfionR3WCBesRIAIA1Ain9Iu9H X-Authority-Analysis: v=2.4 cv=KtdN2XWN c=1 sm=1 tr=0 ts=67f3eed3 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=9rMOtB7ueBl8bWGkC6audQ==:17 a=kj9zAlcOel0A:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=xUTvVhGfsdnD6KsvS_EA:9 a=CjuIK1q_8ugA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: MMSXNWqfionR3WCBesRIAIA1Ain9Iu9H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-07_04,2025-04-03_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504070108 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 07/04/25 17:12:45, neil.armstrong@linaro.org wrote: > On 07/04/2025 16:17, Jorge Ramirez wrote: > > On 07/04/25 14:36:51, neil.armstrong@linaro.org wrote: > > > On 07/04/2025 14:05, Jorge Ramirez-Ortiz wrote: > > > > Select the right clock for sdhci. > > > > > > > > Signed-off-by: Jorge Ramirez-Ortiz > > > > Reviewed-by: Neil Armstrong > > > > --- > > > > drivers/clk/qcom/clock-apq8096.c | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c > > > > index bc00826a5e8..551f52d5197 100644 > > > > --- a/drivers/clk/qcom/clock-apq8096.c > > > > +++ b/drivers/clk/qcom/clock-apq8096.c > > > > @@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate) > > > > struct msm_clk_priv *priv = dev_get_priv(clk->dev); > > > > switch (clk->id) { > > > > - case GCC_SDCC1_APPS_CLK: /* SDC1 */ > > > > + case GCC_SDCC2_APPS_CLK: /* SDC2 */ > > > > > > Should be GCC_SDCC2_AHB_CLK > > > > why? also if I do that, mcc fails to probe > > The discussion at https://lore.kernel.org/all/Z/OqoqnPb1gfk5iG@trex/ made me thought using GCC_SDCC2_AHB_CLK fixed the sdhci set_rate, but I maybe did misread. > > Neil can I add your review/acked? > > > > > > > > > > return clk_init_sdc(priv, rate); > > > > break; > > > > case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/ > > > >