From: Leo Liang <ycliang@andestech.com>
To: Mayuresh Chitale <mchitale@ventanamicro.com>
Cc: <u-boot@lists.denx.de>, Rick Chen <rick@andestech.com>,
Tom Rini <trini@konsulko.com>,
Conor Dooley <conor.dooley@microchip.com>,
"Heinrich Schuchardt" <xypron.glpk@gmx.de>
Subject: Re: [PATCH v1 1/2] riscv: Enhance extension probing
Date: Thu, 16 Jan 2025 15:20:35 +0800 [thread overview]
Message-ID: <Z4izQxsRwiDo4jtC@swlinux02> (raw)
In-Reply-To: <20250106130405.220369-2-mchitale@ventanamicro.com>
On Mon, Jan 06, 2025 at 01:04:04PM +0000, Mayuresh Chitale wrote:
> Enhance the existing extension probing mechanism by adding support for
> more extensions and probing using the "riscv,isa" property. This patch
> is ported from the latest upstream linux.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> ---
> arch/riscv/cpu/cpu.c | 557 ++++++++++++++++++++++++++++
> arch/riscv/include/asm/cpufeature.h | 37 ++
> arch/riscv/include/asm/hwcap.h | 105 ++++++
> 3 files changed, 699 insertions(+)
> create mode 100644 arch/riscv/include/asm/cpufeature.h
> create mode 100644 arch/riscv/include/asm/hwcap.h
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
next prev parent reply other threads:[~2025-01-16 7:20 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-06 13:04 [PATCH v1 0/2] Risc-V ISA Extension Probing Mayuresh Chitale
2025-01-06 13:04 ` [PATCH v1 1/2] riscv: Enhance extension probing Mayuresh Chitale
2025-01-16 7:20 ` Leo Liang [this message]
2025-01-06 13:04 ` [PATCH v1 2/2] riscv: Fallback to riscv,isa Mayuresh Chitale
2025-01-16 7:22 ` Leo Liang
2025-01-06 14:38 ` [PATCH v1 0/2] Risc-V ISA Extension Probing Simon Glass
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